公开(公告)号：GB2566243B

公开(公告)日：2021-02-24

申请号：GB201900535

申请日：2017-05-10

Applicant: IBM

Inventor： CHAO-KUN HU ,  CHRISTIAN LAVOIE ,  STEPHEN ROSSNAGEL ,  THOMAS MCCARROLL SHAW

IPC: H01L21/768 ,  H01L23/532

Abstract: Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a dielectric over a Cu line includes the steps of: forming at least one via in the dielectric over the Cu line; depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic; annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via; and plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier. A device structure is also provided.

公开(公告)号：GB2566243A

公开(公告)日：2019-03-06

申请号：GB201900535

申请日：2017-05-10

Applicant: IBM

Inventor： CHAO-KUN HU ,  CHRISTIAN LAVOIE ,  STEPHEN ROSSNAGEL ,  THOMAS MCCARROLL SHAW

IPC: H01L21/768 ,  H01L23/532

Abstract: Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a dielectric (114) over a Cu line (112) includes the steps of: forming at least one via (116) in the dielectric (114) over the Cu line (112); depositing a metal layer (118) onto the dielectric (114) and lining the via (116) such that the metal layer (118) is in contact with the Cu line (112) at the bottom of the via (116), wherein the metal layer (118) comprises at least one metal that can react with Cu to form a Cu intermetallic; annealing the metal layer (118) and the Cu line (112) under conditions sufficient to form a Cu intermetallic barrier (120) at the bottom of the via (116); and plating Cu (122) into the via (116) to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line (112) by the Cu intermetallic barrier (120). A device structure is also provided.

公开(公告)号：SG118102A1

公开(公告)日：2006-01-27

申请号：SG200107602

申请日：2001-12-07

Applicant: IBM

Inventor： CABRAL CYRIL JR ,  ROY ARTHUR CARRUTHERS ,  JAMES MCKELL EDWIN HARPER ,  CHAO-KUN HU ,  KIM YANG LEE ,  ISMAIL CEVDET NOYAN ,  ROBERT ROSENBERG ,  THOMAS MCCARROLL SHAW

IPC: H01L21/28 ,  B32B15/01 ,  C22C27/02 ,  H01L21/768 ,  H01L23/532 ,  H01L23/485

Abstract: An electrical conductor for use in an electronic structure is disclosed which includes a conductor body that is formed of an alloy including between about 0.001 atomic % and about 2 atomic % of an element selected from the group consisting of Ti, Zr, In, Sn and Hf; and a liner abutting the conductor body which is formed of an alloy that includes Ta, W, Ti, Nb and V. The invention further discloses a liner for use in a semiconductor interconnect that is formed of a material selected from the group consisting of Ti, Hf, In, Sn, Zr and alloys thereof, TiCu3, Ta1-XTix, Ta1-X, Hfx, Ta1-X, Inxy, Ta1-XSnx, Ta1-XZrx.