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1.发明公开METHOD FOR SEPARATELY OPTIMIZING THIN GATE DIELECTRIC OF PMOS AND NMOS TRANSISTORS WITHIN THE SAME SEMICONDUCTOR CHIP AND DEVICE MANUFACTURED THEREBY 审中-公开METHOD FOR SEPARATE OPTIMIZE在同一半导体芯片的PMOS和NMOS晶体管薄栅极电介质，因此生产的设备
公开(公告)号：EP1668696A4
公开(公告)日：2008-09-03
申请号：EP04783206
申请日：2004-09-07
Applicant: IBM
Inventor： CHOU ANTHONY I , FURUKAWA TOSHIHARU , VAREKAMP PATRICK R , SLEIGHT JEFFREY W , SEKIGUCHI AKIHISA
IPC: H01L21/8238
CPC classification number: H01L21/28202 , H01L21/823842 , H01L21/823857
Abstract: A method of forming CMOS semiconductor (10) materials with PFET (16) and NFET (14) areas formed on a semiconductor substrate (12), covered respectively with a PFET (16) and NFET (14) gate dielectric layers composed of silicon oxide and different degrees of nitridation (18D and 18E) thereof. Provide a silicon substrate (12) with a PFET (16) area and an NFET (14) area and form PFET and NFET gate oxide layers thereover. Provide nitridation of the PFET gate oxide layer above the PFET area to form the PFET gate dielectric layer (42) above the PFET area with a first concentration level of nitrogen atoms in the PFET gate dielectric I ayer above the PFET area. Provide nitridation of the NFET gate oxide layer to form the NFET gate dielectric layer (40) above the NFET area with a different concentration level of nitrogen atoms from the first concentration level. The NFET gate dielectric layer (40) and the PFET gate dielectric layer (42) can have the same thickness.
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