公开(公告)号：EP1668696A4

公开(公告)日：2008-09-03

申请号：EP04783206

申请日：2004-09-07

Applicant: IBM

Inventor： CHOU ANTHONY I ,  FURUKAWA TOSHIHARU ,  VAREKAMP PATRICK R ,  SLEIGHT JEFFREY W ,  SEKIGUCHI AKIHISA

IPC: H01L21/8238

CPC classification number: H01L21/28202 ,  H01L21/823842 ,  H01L21/823857

Abstract: A method of forming CMOS semiconductor (10) materials with PFET (16) and NFET (14) areas formed on a semiconductor substrate (12), covered respectively with a PFET (16) and NFET (14) gate dielectric layers composed of silicon oxide and different degrees of nitridation (18D and 18E) thereof. Provide a silicon substrate (12) with a PFET (16) area and an NFET (14) area and form PFET and NFET gate oxide layers thereover. Provide nitridation of the PFET gate oxide layer above the PFET area to form the PFET gate dielectric layer (42) above the PFET area with a first concentration level of nitrogen atoms in the PFET gate dielectric I ayer above the PFET area. Provide nitridation of the NFET gate oxide layer to form the NFET gate dielectric layer (40) above the NFET area with a different concentration level of nitrogen atoms from the first concentration level. The NFET gate dielectric layer (40) and the PFET gate dielectric layer (42) can have the same thickness.

公开(公告)号：EP2409332A4

公开(公告)日：2012-01-25

申请号：EP10753837

申请日：2010-02-11

Applicant: IBM

Inventor： CHOU ANTHONY I ,  FREEMAN GREGORY G ,  MCSTAY KEVIN ,  NARASIMHA SHREESH

IPC: H01L29/739 ,  H01L21/285 ,  H01L21/329 ,  H01L21/33 ,  H01L21/768 ,  H01L27/12

CPC classification number: H01L21/28518 ,  H01L21/76829 ,  H01L29/66356 ,  H01L29/7391

公开(公告)号：JP2007081361A

公开(公告)日：2007-03-29

申请号：JP2006001706

申请日：2006-01-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHAKRAVARTI ASHIMA B ,  CHOU ANTHONY I ,  FURUKAWA TOSHIHARU ,  STEVEN J HOLMES ,  NATZLE WESLEY C

IPC: H01L21/205 ,  H01L21/3065 ,  H01L29/78

CPC classification number: H01L29/7833 ,  H01L21/02532 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/10126 ,  H01L2224/13023 ,  H01L2924/1305 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for selectively accumulating a germanium spacer on a nitride. SOLUTION: In a method for selectively forming a germanium structure in a semiconductor manufacturing process, a native oxide is removed in a chemical oxide removing (COR) process, then surfaces of heated nitride and oxide are exposed to a germanium-containing gas to selectively form the germanium only on the surface of the nitride, not on the surface of the oxide. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在氮化物上选择性地积聚锗间隔物的结构和方法。 解决方案：在半导体制造工艺中选择性地形成锗结构的方法中，在化学氧化物去除（COR）工艺中除去天然氧化物，然后将加热的氮化物和氧化物的表面暴露于含锗气体 以仅选择性地在氮化物的表面上形成锗，而不是在氧化物的表面上形成锗。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2010258471A

公开(公告)日：2010-11-11

申请号：JP2010155374

申请日：2010-07-08

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHANG LELAND ,  CHOU ANTHONY I ,  NARASIMHA SHREESH ,  SLEIGHT JEFFREY W

IPC: H01L29/786 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L29/78615 ,  H01L29/665 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To mount a body contact on a semiconductor-on-insulator device, thereby reducing parasitic capacitance in the device. SOLUTION: A substrate includes a semiconductor layer arranged so as to be covered on an insulating layer. The semiconductor layer includes the substrate including a semiconductor body and an separation region existing around the outer periphery of the semiconductor body, and a gate structure covered on the semiconductor layer of the substrate. A method for manufacturing a semiconductor device is provided. The semiconductor device includes the gate structure existing on a first part of an upper face of the semiconductor body and a silicide body contact directly physically brought into contact with a second part of the semiconductor body separated from the first part of the semiconductor body by a non-silicide semiconductor region. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：将绝缘体上的半导体器件接触，从而减少器件中的寄生电容。 解决方案：衬底包括布置成被覆盖在绝缘层上的半导体层。 半导体层包括包括半导体本体的基板和存在于半导体主体的外周周围的分离区域，以及覆盖在基板的半导体层上的栅极结构。 提供一种制造半导体器件的方法。 该半导体器件包括存在于半导体本体的上表面的第一部分上的栅极结构和直接物理地与半导体本体的第一部分分离的半导体主体的第二部分接触的硅化物体接触， 硅化物半导体区域。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2010004006A

公开(公告)日：2010-01-07

申请号：JP2008259405

申请日：2008-10-06

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHANG LELAND ,  CHOU ANTHONY I ,  NARASIMHA SHREESH ,  SLEIGHT JEFFREY W

IPC: H01L29/786

CPC classification number: H01L29/78615 ,  H01L29/665 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To reduce the parasitic capacitance of an semiconductor-on-insulator device by providing the semiconductor-on-insulator device with a body contact. SOLUTION: In one embodiment, the invention provides a semiconductor device that includes: a substrate including a semiconductor layer positioned overlaying an insulating layer, the semiconducting layer including a semiconducting body and isolation regions present around a perimeter of the semiconducting body; a gate structure overlaying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：通过提供绝缘体上半导体器件与体接触来减小绝缘体上半导体器件的寄生电容。 解决方案：在一个实施例中，本发明提供了一种半导体器件，其包括：衬底，其包括覆盖绝缘层的半导体层，所述半导体层包括半导体本体和围绕半导体本体的周边存在的隔离区; 覆盖所述衬底的半导体层的栅极结构，所述栅极结构存在于所述半导体本体的上表面上的第一部分上; 以及通过非硅化物半导体区域与半导电体的第一部分分离的与半导体的第二部分直接物理接触的硅化物体接触。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2004048001A

公开(公告)日：2004-02-12

申请号：JP2003183483

申请日：2003-06-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BURNHAM JAY S ,  CHOU ANTHONY I ,  FURUKAWA TOSHIHARU ,  MARGARET L GIBSON ,  NAKOS JAMES S ,  SHANK STEVEN M

IPC: H01L21/318 ,  H01L21/28 ,  H01L21/314 ,  H01L21/324 ,  H01L21/336 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/28194 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/324 ,  H01L29/4908 ,  H01L29/518 ,  H01L29/66757

Abstract: PROBLEM TO BE SOLVED: To provide a highly reliable gate insulation film with respect to a gate insulation film forming method by silicon nitride oxide. SOLUTION: The gate insulation film forming method includes a process for preparing a substrate, a process for forming a silicon dioxide layer on the top surface of the substrate, a process for exposing the silicon dioxide layer to a plasma-nitride forming process in order to change the silicon dioxide layer into a silicon nitride oxide layer, and a process for subjecting the silicon nitride oxide layer to spike-like rapid annealing. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2002324903A

公开(公告)日：2002-11-08

申请号：JP2002068920

申请日：2002-03-13

Applicant: IBM

Inventor： KHARE MUKESH ,  AGNELLO PAUL D ,  CHOU ANTHONY I ,  HOOK TERENCE B ,  MOCUTA ANDA C

IPC: H01L21/74 ,  H01L29/423 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method and circuit configuration effective for reducing plasma-induced charging damage on a device fabricated on a silicon-on- insulator(SOI) substrate. SOLUTION: An SOI circuit configuration effective for minimizing plasma- induced charging damage during fabrication comprises formation of charge collectors connected to the gate electrode and a semiconductor body, wherein each of the charge collectors has the same or substantially the same shape and dimension. The formation of a connecting structure between a device formed on the SOI substrate and the substrate is delayed until the later stages of processing.