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    Field effect transistor (fet) inverter and method of fabricating the same (nanowire mesh of single gate inverter)
    4.
    发明专利
    Field effect transistor (fet) inverter and method of fabricating the same (nanowire mesh of single gate inverter) 有权
    场效应晶体管（FET）逆变器及其制造方法（单门逆变器的纳米网）

    公开(公告)号：JP2010272859A

    公开(公告)日：2010-12-02

    申请号：JP2010108180

    申请日：2010-05-10

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CHANG JOSEPHINE B ,  GUILLORN MICHAEL A ,  SLEIGHT JEFFREY W ,  CHANG PAUL

    IPC: H01L29/786 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

    CPC classification number: H01L27/1203 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78696 ,  Y10S977/762 ,  Y10S977/938

    Abstract: PROBLEM TO BE SOLVED: To provide a nanowire mesh of a single gate inverter and a method of fabricating the same. SOLUTION: The field effect transistor (FET) includes a plurality of device layers disposed vertically in a stack, each device layer has a source region, a drain region and a plurality of nanowire channels 110 connecting the source region and the drain region, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant or a p-type dopant. The FET inverter further includes a common gate 150 surrounding the plurality of nanowire channels, a first contact 156 to the source regions of the one or more device layers doped with the n-type dopant, a second contact 158 to the source regions of the one or more device layers doped with the p-type dopant, and a common third contact 152 to the drain regions of each of the device layers. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供单栅极逆变器的纳米线网及其制造方法。 解决方案：场效应晶体管（FET）包括在堆叠中垂直设置的多个器件层，每个器件层具有源极区，漏极区和连接源极区和漏极区的多个纳米线通道110 其中一个或多个器件层的源区和漏区掺杂有n型掺杂剂或p型掺杂剂。 FET反相器还包括围绕多个纳米线通道的公共栅极150，向掺杂有n型掺杂剂的一个或多个器件层的源极区域提供的第一接触156，一个或多个纳米线通道的源极区域的第二接触158 或更多的掺杂有p型掺杂剂的器件层，以及与每个器件层的漏极区域的公共第三接触152。 版权所有（C）2011，JPO＆INPIT

    Method and structure for soi body contact fet with reduced parasitic capacitance
    5.
    发明专利
    Method and structure for soi body contact fet with reduced parasitic capacitance 审中-公开
    具有降低PARASITIC电容的SOI体接触FET的方法和结构

    公开(公告)号：JP2010004006A

    公开(公告)日：2010-01-07

    申请号：JP2008259405

    申请日：2008-10-06

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CHANG LELAND ,  CHOU ANTHONY I ,  NARASIMHA SHREESH ,  SLEIGHT JEFFREY W

    IPC: H01L29/786

    CPC classification number: H01L29/78615 ,  H01L29/665 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To reduce the parasitic capacitance of an semiconductor-on-insulator device by providing the semiconductor-on-insulator device with a body contact. SOLUTION: In one embodiment, the invention provides a semiconductor device that includes: a substrate including a semiconductor layer positioned overlaying an insulating layer, the semiconducting layer including a semiconducting body and isolation regions present around a perimeter of the semiconducting body; a gate structure overlaying the semiconducting layer of the substrate, the gate structure present on a first portion on an upper surface of the semiconducting body; and a silicide body contact that is in direct physical contact with a second portion of the semiconducting body that is separated from the first portion of the semiconducting body by a non-silicide semiconducting region. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：通过提供绝缘体上半导体器件与体接触来减小绝缘体上半导体器件的寄生电容。 解决方案：在一个实施例中，本发明提供了一种半导体器件，其包括：衬底，其包括覆盖绝缘层的半导体层，所述半导体层包括半导体本体和围绕半导体本体的周边存在的隔离区; 覆盖所述衬底的半导体层的栅极结构，所述栅极结构存在于所述半导体本体的上表面上的第一部分上; 以及通过非硅化物半导体区域与半导电体的第一部分分离的与半导体的第二部分直接物理接触的硅化物体接触。 版权所有（C）2010，JPO＆INPIT

    Method for soi body contact fet with reduced parasitic capacitance
    6.
    发明专利
    Method for soi body contact fet with reduced parasitic capacitance 有权
    具有降低的PARASIIC电容的SOI体接触FET的方法

    公开(公告)号：JP2010258471A

    公开(公告)日：2010-11-11

    申请号：JP2010155374

    申请日：2010-07-08

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CHANG LELAND ,  CHOU ANTHONY I ,  NARASIMHA SHREESH ,  SLEIGHT JEFFREY W

    IPC: H01L29/786 ,  H01L21/768 ,  H01L23/522

    CPC classification number: H01L29/78615 ,  H01L29/665 ,  H01L29/66772 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To mount a body contact on a semiconductor-on-insulator device, thereby reducing parasitic capacitance in the device. SOLUTION: A substrate includes a semiconductor layer arranged so as to be covered on an insulating layer. The semiconductor layer includes the substrate including a semiconductor body and an separation region existing around the outer periphery of the semiconductor body, and a gate structure covered on the semiconductor layer of the substrate. A method for manufacturing a semiconductor device is provided. The semiconductor device includes the gate structure existing on a first part of an upper face of the semiconductor body and a silicide body contact directly physically brought into contact with a second part of the semiconductor body separated from the first part of the semiconductor body by a non-silicide semiconductor region. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：将绝缘体上的半导体器件接触，从而减少器件中的寄生电容。 解决方案：衬底包括布置成被覆盖在绝缘层上的半导体层。 半导体层包括包括半导体本体的基板和存在于半导体主体的外周周围的分离区域，以及覆盖在基板的半导体层上的栅极结构。 提供一种制造半导体器件的方法。 该半导体器件包括存在于半导体本体的上表面的第一部分上的栅极结构和直接物理地与半导体本体的第一部分分离的半导体主体的第二部分接触的硅化物体接触， 硅化物半导体区域。 版权所有（C）2011，JPO＆INPIT

    METHOD FOR SEPARATELY OPTIMIZING THIN GATE DIELECTRIC OF PMOS AND NMOS TRANSISTORS WITHIN THE SAME SEMICONDUCTOR CHIP AND DEVICE MANUFACTURED THEREBY
    9.
    发明公开
    METHOD FOR SEPARATELY OPTIMIZING THIN GATE DIELECTRIC OF PMOS AND NMOS TRANSISTORS WITHIN THE SAME SEMICONDUCTOR CHIP AND DEVICE MANUFACTURED THEREBY 审中-公开
    METHOD FOR SEPARATE OPTIMIZE在同一半导体芯片的PMOS和NMOS晶体管薄栅极电介质，因此生产的设备

    公开(公告)号：EP1668696A4

    公开(公告)日：2008-09-03

    申请号：EP04783206

    申请日：2004-09-07

    Applicant: IBM

    Inventor： CHOU ANTHONY I ,  FURUKAWA TOSHIHARU ,  VAREKAMP PATRICK R ,  SLEIGHT JEFFREY W ,  SEKIGUCHI AKIHISA

    IPC: H01L21/8238

    CPC classification number: H01L21/28202 ,  H01L21/823842 ,  H01L21/823857

    Abstract: A method of forming CMOS semiconductor (10) materials with PFET (16) and NFET (14) areas formed on a semiconductor substrate (12), covered respectively with a PFET (16) and NFET (14) gate dielectric layers composed of silicon oxide and different degrees of nitridation (18D and 18E) thereof. Provide a silicon substrate (12) with a PFET (16) area and an NFET (14) area and form PFET and NFET gate oxide layers thereover. Provide nitridation of the PFET gate oxide layer above the PFET area to form the PFET gate dielectric layer (42) above the PFET area with a first concentration level of nitrogen atoms in the PFET gate dielectric I ayer above the PFET area. Provide nitridation of the NFET gate oxide layer to form the NFET gate dielectric layer (40) above the NFET area with a different concentration level of nitrogen atoms from the first concentration level. The NFET gate dielectric layer (40) and the PFET gate dielectric layer (42) can have the same thickness.

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