公开(公告)号：JP2007329489A

公开(公告)日：2007-12-20

申请号：JP2007176125

申请日：2007-07-04

Applicant: Infineon Technologies Ag ,  インフィニオン テクノロジーズ アクチエンゲゼルシャフトInfineon Technologies Ag

Inventor： ROESNER WOLFGANG ,  HOFMANN FRANZ ,  BERTAGNOLLI EMMERICH ,  GOEBEL BERND

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/336 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/088 ,  H01L27/105 ,  H01L27/108 ,  H01L27/112

CPC classification number: H01L27/10876 ,  H01L27/1052 ,  H01L27/10823 ,  H01L27/112 ,  H01L27/11273

Abstract: PROBLEM TO BE SOLVED: To provide a high-density integrated circuit device by which a floating body effect of a transistor can be avoided.
SOLUTION: A vertical MOS transistor includes a series of layers SF, SF* arranged on a first conductive type substrate 1. The series of layers comprise a lower layer U for a first source/drain region, an intermediate layer M doped with a first conductive type to act as a channel region, and an upper layer O for a second source/drain region. A connection structure V doped with the first conductive type is arranged on a first surface of the series of layers SF, SF* to electrically connect the channel region to the substrate 1. A gate electrode of the transistor is arranged on a second surface of the series of layers SF, SF*. The connection structure V can be arranged between the series of layers SF, SF* and the same or another series of layers SF, SF*. The dimension of the connection structure V or the like can be a lithography dimension or less. The manufactured circuit is suitable for a storage cell arrangement.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供可以避免晶体管的浮体效应的高密度集成电路器件。 解决方案：垂直MOS晶体管包括布置在第一导电型衬底1上的一系列层SF，SF *。一系列层包括用于第一源/漏区的下层U，掺杂有 用作沟道区的第一导电类型和用于第二源极/漏极区的上层O。 掺杂有第一导电类型的连接结构V布置在一系列层SF，SF *的第一表面上，以将沟道区域电连接到衬底1.晶体管的栅极布置在第二表面上 系列SF，SF *。 连接结构V可以布置在一系列层SF，SF *和相同或另一系列层SF，SF *之间。 连接结构V等的尺寸可以是光刻尺寸或更小。 制造的电路适用于存储单元布置。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：DE59711121D1

公开(公告)日：2004-01-29

申请号：DE59711121

申请日：1997-05-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOM FELDE ANDREAS ,  BERTAGNOLLI EMMERICH ,  KERBER MARTIN

IPC: G01N27/414 ,  G01N27/327 ,  G01N27/416 ,  G01N33/487 ,  G06N3/00 ,  H01L29/78

Abstract: An MOS transistor has a gate electrode is electrically conductively connected to an exposed contact area (pad). The contact area is electrochemically corrosion-resistant and is dimensioned for connection to a living cell. The surface topology is relatively flat and the surface, with the exception of the contact area, is protected with a dielectric passivation layer.

公开(公告)号：DE50014238D1

公开(公告)日：2007-05-24

申请号：DE50014238

申请日：2000-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WILLER JOSEF ,  SCHLOESSER TILL ,  BERTAGNOLLI EMMERICH

IPC: H01L21/02

Abstract: A dynamic random access memory capacitor and to a method for producing the same are described. A first (bottom) electrode of the capacitor has a grained surface made of tungsten silicide placed on a tungsten silicide layer which is disposed near a surface of a electrode body. The graining of the tungsten silicide layer is formed by tempering a temporarily present double layer that is formed of an understoichiometric tungsten silicide layer and a silicon layer. The double layer is formed on the tungsten silicide layer.

公开(公告)号：DE19727466C2

公开(公告)日：2001-12-20

申请号：DE19727466

申请日：1997-06-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  BERTAGNOLLI EMMERICH

IPC: G11C11/34 ,  G11C11/405 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/401

Abstract: The cell has three transistors e.g. vertical transistors formed on the edges (1F1,1F2,2F2) of trenches (G1,G2) separated alternately by smaller and larger gaps. These facilitate the interconnection of source/drain regions (1S/D1,3S/D2, 2S/D2) of different transistors by contact regions (K). A gate electrode (Ga1) of one transistor is connected to a wordline which is to be read (WA), with the second source or drain region (1S/D2) of this transistor being connected to a bitline (B). The gate electrode (Ga3) of a third transistor is connected to a wordline which is to be written to. The first source or drain region (1S/D1) of the reading transistor is connected to both the second source/drain region of the writing transistor and to which a source/drain region (2S/D2) of a further transistor. The gate (Ga2) of this latter transistor is connected to the source/drain (3S/D1) of the writing transistor and its other source/drain is connected to a power supply.

公开(公告)号：DE59809504D1

公开(公告)日：2003-10-09

申请号：DE59809504

申请日：1998-06-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  BERTAGNOLLI EMMERICH ,  WILLER JOSEF ,  HASLER BARBARA ,  VON BASSE PAUL-WERNER

IPC: H01L21/8244 ,  H01L27/11

公开(公告)号：DE59904972D1

公开(公告)日：2003-05-15

申请号：DE59904972

申请日：1999-07-01

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  JACOBS HERMANN ,  SCHWARZL SIEGFRIED ,  BERTAGNOLLI EMMERICH

IPC: G11C11/14 ,  G11C11/00 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22

Abstract: A storage cell is described which includes a storage element whose electric resistance represents an information unit and can be influenced by a magnetic field as well as a transistor which when the information is read out allows for the corresponding storage cell to be selected from among the storage cells. To write the information unit, a write line and a bit line are provided which intersect in the area of the storage element and are able to generate the magnetic field. The storage cell is disposed between the bit line and a shared voltage supply connection. The storage cell is disposed between the bit line and the write line and the write line can coincide with a gate line that controls the transistor. The transistor is a planar or vertical transistor. The storage element and the transistor can be positioned next to or on top of each other.

公开(公告)号：DE19720193C2

公开(公告)日：2002-10-17

申请号：DE19720193

申请日：1997-05-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOEBEL BERND ,  BERTAGNOLLI EMMERICH

IPC: H01L21/8238 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234

Abstract: An integrated circuit having at least two vertical MOS transistors, and method for manufacturing same, wherein first source/drain regions of the two vertical MOS transistors are located in an upper region of sidewalls of a trench. A second source/drain region is shared by both MOS transistors and is adjacent a floor of the trench. Gate electrodes of the MOS transistors that are arranged at the sidewalls of the trench can be individually contacted via parts of a conductive layer that are arranged above the first source/drain regions. In a manufacturing method, such arrangement is made possible by the deposition of a conductive layer of doped polysilicon before the generation of the trench. The area of an MOS transistor can amount to 4F2.