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    Integrated circuit device and method of manufacturing the same
    1.
    发明专利
    Integrated circuit device and method of manufacturing the same 有权
    集成电路装置及其制造方法

    公开(公告)号：JP2007329489A

    公开(公告)日：2007-12-20

    申请号：JP2007176125

    申请日：2007-07-04

    Applicant: Infineon Technologies Ag ,  インフィニオン テクノロジーズ アクチエンゲゼルシャフトInfineon Technologies Ag

    Inventor： ROESNER WOLFGANG ,  HOFMANN FRANZ ,  BERTAGNOLLI EMMERICH ,  GOEBEL BERND

    IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/336 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/088 ,  H01L27/105 ,  H01L27/108 ,  H01L27/112

    CPC classification number: H01L27/10876 ,  H01L27/1052 ,  H01L27/10823 ,  H01L27/112 ,  H01L27/11273

    Abstract: PROBLEM TO BE SOLVED: To provide a high-density integrated circuit device by which a floating body effect of a transistor can be avoided.
    SOLUTION: A vertical MOS transistor includes a series of layers SF, SF* arranged on a first conductive type substrate 1. The series of layers comprise a lower layer U for a first source/drain region, an intermediate layer M doped with a first conductive type to act as a channel region, and an upper layer O for a second source/drain region. A connection structure V doped with the first conductive type is arranged on a first surface of the series of layers SF, SF* to electrically connect the channel region to the substrate 1. A gate electrode of the transistor is arranged on a second surface of the series of layers SF, SF*. The connection structure V can be arranged between the series of layers SF, SF* and the same or another series of layers SF, SF*. The dimension of the connection structure V or the like can be a lithography dimension or less. The manufactured circuit is suitable for a storage cell arrangement.
    COPYRIGHT: (C)2008,JPO&INPIT

    Abstract translation: 要解决的问题：提供可以避免晶体管的浮体效应的高密度集成电路器件。 解决方案：垂直MOS晶体管包括布置在第一导电型衬底1上的一系列层SF，SF *。一系列层包括用于第一源/漏区的下层U，掺杂有 用作沟道区的第一导电类型和用于第二源极/漏极区的上层O。 掺杂有第一导电类型的连接结构V布置在一系列层SF，SF *的第一表面上，以将沟道区域电连接到衬底1.晶体管的栅极布置在第二表面上 系列SF，SF *。 连接结构V可以布置在一系列层SF，SF *和相同或另一系列层SF，SF *之间。 连接结构V等的尺寸可以是光刻尺寸或更小。 制造的电路适用于存储单元布置。 版权所有（C）2008，JPO＆INPIT

    SEMICONDUCTOR MEMORY WITH MEMORY CELLS COMPRISING A VERTICAL SELECTION TRANSISTOR AND METHOD FOR PRODUCTION THEREOF
    2.
    发明申请
    SEMICONDUCTOR MEMORY WITH MEMORY CELLS COMPRISING A VERTICAL SELECTION TRANSISTOR AND METHOD FOR PRODUCTION THEREOF 审中-公开
    包含垂直选择晶体管的具有存储器单元的半导体存储器及其制造方法

    公开(公告)号：WO03028104A3

    公开(公告)日：2003-08-14

    申请号：PCT/DE0202980

    申请日：2002-08-14

    Applicant: INFINEON TECHNOLOGIES AG ,  LUETZEN JOERN ,  GOEBEL BERND ,  SCHUMANN DIRK ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  POPP MARTIN ,  KERSCH ALFRED ,  STEINHOEGL WERNER

    Inventor： LUETZEN JOERN ,  GOEBEL BERND ,  SCHUMANN DIRK ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  POPP MARTIN ,  KERSCH ALFRED ,  STEINHOEGL WERNER

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L27/10891

    Abstract: A trench capacitor (30) is arranged in a first trench (25) for production of a semiconductor memory (5). A first longitudinal trench (55) is arranged in the substrate (15) next to the first trench (25) and parallel thereto on the other side of the first trench (25), a second longitudinal trench (60) is arranged therein. A first spacer word line (70) is arranged in the first longitudinal trench (55) and a second spacer word line (75) is arranged in the second longitudinal trench (60). Connecting webs (80) are arranged in the first trench (25) between the first spacer word line (70) and the second spacer word line (75) with a thickness (110), which is smaller in the direction of the first spacer word line (70) than half the width of the first trench (25) in the direction of the first spacer word line (70).

    Abstract translation: 为了制造半导体存储器（5），沟槽电容器（30）被布置在第一沟槽（25）中。 除了所述第一沟槽（25），第一纵向沟槽（55）和上第一沟槽并行（25），在所述基板的第二纵向沟槽（60）的另一侧（15）被布置。 在第一纵向沟槽（55）中设置第一间隔字线（70），在第二纵向沟槽（60）中设置第二间隔字线（75）。 在所述第一沟槽（25）的连接板（80）设置在所述第一间隔物的字线（70）和具有厚度（110）所述第二间隔的字线（75）（在第一间隔的字线70的方向之间 ）小于第一沟槽（25）朝向第一间隔字线（70）的宽度的一半。

    SEMICONDUCTOR MEMORY CELL ARRANGEMENT AND METHOD FOR PRODUCING THE SAME
    4.
    发明申请
    SEMICONDUCTOR MEMORY CELL ARRANGEMENT AND METHOD FOR PRODUCING THE SAME 审中-公开
    半导体存储器单元装置和方法及其

    公开(公告)号：WO0211200A8

    公开(公告)日：2002-04-11

    申请号：PCT/DE0102798

    申请日：2001-07-23

    Applicant: INFINEON TECHNOLOGIES AG ,  GOEBEL BERND ,  LUETZEN JOERN ,  POPP MARTIN ,  SEIDL HARALD

    Inventor： GOEBEL BERND ,  LUETZEN JOERN ,  POPP MARTIN ,  SEIDL HARALD

    IPC: H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10864

    Abstract: The invention relates to a semiconductor memory cell arrangement comprising dynamic memory cells (10) which each have a trench capacitor (1) and a vertical selection transistor (2). Said vertical selection transistor (2) is situated essentially above the trench capacitor (1) and has a series of layers which is offset from the inner electrode of the trench capacitor (1) and which is connected to said inner electrode (11) of the trench capacitor (1). An active intermediate layer (22) is completely surrounded by an insulator layer (24) and a gate electrode layer (25) which is connected to a word line (7). The dynamic memory cells (10) are arranged in the form of a matrix, the trench capacitors (1) and the corresponding vertical selection transistors (2) of the dynamic memory cells (10) succeeding each other in a line and/or column sequence, respectively.

    Abstract translation: 具有动态存储单元的半导体存储器单元阵列（10），每一个都具有严重的电容器（1）和一个verikalen选择晶体管（2），其特征在于，垂直选择晶体管（2）基本上高于WOM严重电容器（1）被布置和相对的内部电极 被严重电容器（1）与一个布置成与严重电容器（1），其特征在于，有源中间层（22）被封闭具有完全的绝缘体层（24）和栅电极层（25）的内电极（11）偏移的层序列 Worleitung（7）连接，其中，所述动态存储单元（10）被布置成矩阵，和坟墓电容器（1）和相关联的垂直选择Transistore（2）的动态存储器单元（10），每行和/或列状连续的。

    METHOD FOR THE PRODUCTION OF AN INTEGRATED SEMICONDUCTOR CIRCUIT
    5.
    发明申请
    METHOD FOR THE PRODUCTION OF AN INTEGRATED SEMICONDUCTOR CIRCUIT 审中-公开
    生产集成半导体电路的方法

    公开(公告)号：WO2004030028A3

    公开(公告)日：2004-06-03

    申请号：PCT/DE0303068

    申请日：2003-09-16

    Applicant: INFINEON TECHNOLOGIES AG ,  GOEBEL BERND ,  MOLL PETER ,  SCHUMANN DIRK ,  SEIDL HARALD

    Inventor： GOEBEL BERND ,  MOLL PETER ,  SCHUMANN DIRK ,  SEIDL HARALD

    IPC: H01L20060101 ,  H01L21/768 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10888 ,  H01L21/76895 ,  H01L27/10864 ,  H01L27/10894

    Abstract: The invention relates to a method for the production of an integrated semiconductor circuit, whereby electrical contacts (20), for first conducting structures (1), are produced in the memory region (I) and the first conducting structures (1) are contacted, without contacting second conducting structures (2) arranged laterally with respect to the first conducting structures (1), which laterally border the first conducting structures (1) or are arranged too close to the same to be selectively lithographically masked. According to the invention, the first conducting structures (1) are contacted, whereby a conducting layer (L) is deposited and structured after a planarisation in the memory region at the level of the first conducting structures (1) above the second conducting structures (2), which is applied in the logic region for the generation of gate electrodes, for example. Intermediate contacts (10) are thus structured which are so wide that contact holes for the electrical contacts can be fitted thereon. The deposition of a nitride layer for the protection of the second conducting layer (2) is thus superfluous.

    Abstract translation: 本发明涉及一种用于制造在其中为第一导电结构（1）的存储器区域（I）（20）制备的半导体集成电路的电接触，并且所述第一导电结构（1）由所述第一结构没有横向导电接触 （2）（1）设置在第二导电图案，以接触施加于第一导电图案的侧面（1）抵接或挨着它们紧密地布置成选择性地掩蔽以它们能够光刻。 根据本发明，第一导电结构（1）由所述存储区域在已经在所述逻辑区域被使用过的第二导电结构（2）平坦化，导电层（L）后上面的第一导电结构（1）的电平相接触，例如用于生产栅电极的 变得分离和结构化。 这个中间触点（10）是结构化的，其宽度足以使电触点（20）的触点孔可以调节到它们。 不需要沉积氮化物层以保护第二导电结构（2）。

    7.
    发明专利
    未知

    公开(公告)号：DE50012981D1

    公开(公告)日：2006-07-27

    申请号：DE50012981

    申请日：2000-08-08

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GOEBEL BERND

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: A depression is produced in a substrate for a capacitor of a memory cell of the DRAM cell configuration. An insulation and a storage node of the capacitor are produced in the depression. A spacer made of silicon is produced above the storage node. A first part of the spacer is doped by inclined implantation. The spacer is patterned by utilizing the different doping of the first part of the spacer. With the aid of the patterned spacer as a mask, the storage node and the insulation are altered in such a way that the storage node directly adjoins the substrate only in a limited patch of a sidewall of the depression and is otherwise isolated from the substrate by the insulation.

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