HUMIDITY SENSOR
    1.
    发明申请
    HUMIDITY SENSOR 审中-公开
    湿度传感器

    公开(公告)号:WO0111347A3

    公开(公告)日:2001-11-01

    申请号:PCT/EP0007804

    申请日:2000-08-10

    CPC classification number: G01N27/223

    Abstract: A semiconductor sensor (2) comprising a capacitively sensitive surface (3) is placed in the area of a gas atmosphere. The semiconductor sensor (2) can be cooled by a cooling device (5). The current temperature of the semiconductor sensor (2) is determined using a cooling temperature sensor (7) as liquid (14) condenses on the capacitively sensitive surface (3). The air humidity of the gas atmosphere is subsequently determined using said current temperature and the temperature of the gas atmosphere.

    Abstract translation: 具有电容敏感表面(3)的半导体传感器(2)设置在气体区域中。 半导体传感器(2)可以通过冷却装置(5)冷却。 利用冷却温度传感器(7),确定液体(14)在电容敏感表面(3)上凝结期间半导体传感器(2)的瞬时温度。 这和气体气氛的温度,然后确定气体气氛的空气湿度。

    2.
    发明专利
    未知

    公开(公告)号:DE59913479D1

    公开(公告)日:2006-07-06

    申请号:DE59913479

    申请日:1999-02-22

    Abstract: The process involves pre-loading all bit lines to the blocking potential (VB) with the blocking decoder. All outputs of the word decoder are set to a protective voltage (VS) so all memory cells of the cell field are conducting and the blocking potential is carried over to the entire cell field. The blocking decoder is completely decoupled from the cell field so the blocking potential remains stored on the capacitors of the bit lines (BL). The bit decoder is switched on and connects a bit line with the line which holds the information value to be programmed. The information is transferred to the bit line. A word line is selected via the word decoder and set to the programming potential (VP). The memory cell is programmed, at the crossing point of the word line with the previously chosen bit line. Finally the word and bit decoder are switched off.

    5.
    发明专利
    未知

    公开(公告)号:ES2173760T3

    公开(公告)日:2002-10-16

    申请号:ES99952375

    申请日:1999-08-12

    Abstract: A grid-shaped array of conductor areas is used for capacitive image acquisition. Shielding conductors are disposed in each case between the conductors that are provided for measurement. During a plurality of charging and discharging cycles, the potential is always carried along on the conductors belonging to a respective pixel in order to prevent displacement currents between the shielding capacitors. By way of example, a compensation line with a feedback operational amplifier can be used for identically altering the electrical potentials on the conductors.

    6.
    发明专利
    未知

    公开(公告)号:AT214179T

    公开(公告)日:2002-03-15

    申请号:AT99952375

    申请日:1999-08-12

    Abstract: A grid-shaped array of conductor areas is used for capacitive image acquisition. Shielding conductors are disposed in each case between the conductors that are provided for measurement. During a plurality of charging and discharging cycles, the potential is always carried along on the conductors belonging to a respective pixel in order to prevent displacement currents between the shielding capacitors. By way of example, a compensation line with a feedback operational amplifier can be used for identically altering the electrical potentials on the conductors.

    8.
    发明专利
    未知

    公开(公告)号:DE59900961D1

    公开(公告)日:2002-04-11

    申请号:DE59900961

    申请日:1999-08-12

    Abstract: A grid-shaped array of conductor areas is used for capacitive image acquisition. Shielding conductors are disposed in each case between the conductors that are provided for measurement. During a plurality of charging and discharging cycles, the potential is always carried along on the conductors belonging to a respective pixel in order to prevent displacement currents between the shielding capacitors. By way of example, a compensation line with a feedback operational amplifier can be used for identically altering the electrical potentials on the conductors.

    9.
    发明专利
    未知

    公开(公告)号:DE59608187D1

    公开(公告)日:2001-12-20

    申请号:DE59608187

    申请日:1996-08-30

    Abstract: The matrix includes memory cells (1), each memory cell is provided with a MOSFET (10), and arranged in rows (2) and columns (3). The matrix columns lie between two adjacent bit lines (4) and selection lines (5) extend along each row. The selection lines are also connected to the gate of each memory cell transistor along respective line. An auxiliary MOSFET (20) is connected via its source and drain terminals to the adjacent bit lines, or to one bit line and a given potential. The gate electrode of this MOSFET coupled to a common bias line (6), allowing the bit lines to be selectively brought to a given potential.

Patent Agency Ranking