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    METHOD FOR MANUFACTURING CONDUCTING CONNECTION
    1.
    发明专利
    METHOD FOR MANUFACTURING CONDUCTING CONNECTION 审中-公开

    公开(公告)号：JP2002141412A

    公开(公告)日：2002-05-17

    申请号：JP2001255934

    申请日：2001-08-27

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HASLER BARBARA ,  SCHNABEL RAINER FLORIAN ,  SCHINDLER GUENTHER DR ,  WEINRICH VOLKER

    IPC: H01L23/522 ,  H01L21/02 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

    Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a conducting connection which permits the number of processes to be held as small as possible, or rather to be reduced, without such problems as overetching of trenches and dielectric close-off. SOLUTION: A semiconductor substrate having at least one insulation layer is prepared. A mask is formed on the upper face of the insulation layer, and then an isotropic etching process is mainly conducted, and then an anisotropic etching is mainly conducted until reaching the lower face of the insulation film and thereby forming a contact hole. Then, the mask is removed and the contact hole is filled with a first conductive material. The first conductive material is etched back to a specified depth, and then a free region of the contact hole is filled with at least one kind of second conductive material.

    3.
    发明专利
    未知

    公开(公告)号：DE102007019552A1

    公开(公告)日：2008-10-30

    申请号：DE102007019552

    申请日：2007-04-25

    Applicant: QIMONDA AG ,  INFINEON TECHNOLOGIES AG

    Inventor： DERTINGER STEPHAN ,  MARTIN ALFRED ,  HASLER BARBARA ,  SOMMER GRIT ,  BINDER FLORIAN

    IPC: H01L21/60 ,  H01L23/50

    Abstract: A substrate with first and second main surfaces includes at least one channel extending from the first main surface to the second main surface. The at least one channel includes a first cross-sectional area at a first location and a second cross-sectional area at a second location. An electrically conductive first material is disposed in the at least one channel.

    4.
    发明专利
    未知

    公开(公告)号：DE102007019552B4

    公开(公告)日：2009-12-17

    申请号：DE102007019552

    申请日：2007-04-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： DERTINGER STEPHAN ,  MARTIN ALFRED ,  HASLER BARBARA ,  SOMMER GRIT ,  BINDER FLORIAN

    IPC: H01L21/60 ,  H01L23/12 ,  H01L23/50

    Abstract: A substrate with first and second main surfaces includes at least one channel extending from the first main surface to the second main surface. The at least one channel includes a first cross-sectional area at a first location and a second cross-sectional area at a second location. An electrically conductive first material is disposed in the at least one channel.

    5.
    发明专利
    未知

    公开(公告)号：DE102008044381A1

    公开(公告)日：2009-07-23

    申请号：DE102008044381

    申请日：2008-12-05

    Applicant: INFINEON TECHNOLOGIES AG ,  QIMONDA AG

    Inventor： FRANOSCH MARTIN ,  HASLER BARBARA ,  MARTIN ALFRED ,  OPPERMANN KLAUS-GUENTER

    IPC: H01L21/60 ,  H01L23/488

    Abstract: An integrated circuit that comprises a substrate and a structured layer on the substrate. The structured layer comprises an opening to the substrate, a first field and a second field on the substrate, wherein the first field and the second field, at least in part, overlap with the opening. The integrated circuit further comprises a first material in the area of the first field and a second material in the area of the second field. The first material impedes a wetting by a solder material, and the second provides a wetting by the solder material.

    7.
    发明专利
    未知

    公开(公告)号：DE10042235A1

    公开(公告)日：2002-04-18

    申请号：DE10042235

    申请日：2000-08-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHINDLER GUENTHER ,  HASLER BARBARA ,  SCHNABEL R FLORIAN ,  WEINRICH VOLKER

    IPC: H01L23/522 ,  H01L21/02 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/283

    Abstract: Process for forming an electrically conducting connection between a diffusion region and an electrode (70). Process comprises: (i) preparing a semiconductor substrate with an insulating layer; (ii) applying a mask (65) to the surface of the insulating layer; (iii) isotropically etching; (iv) anisotropically etching until the lower side of the insulating layer is reached and forming a contact hole (6); (v) removing the mask; (vi) filling the hole with a first conducting material; (vii) back etching the conducting material; and (viii) filling the contact hole with as second conducting material. Preferred Features: The ratio of the contact hole surface in the isotropically etched region to the contact hole surface in the anisotropically etched region is 1.5-4, preferably 2-3. An adhesion promoting layer (62) made of titanium, titanium nitride, titanium silicide, tantalum nitride or tantalum silicon nitride is produced between the two conducting layers.

    8.
    发明专利
    未知

    公开(公告)号：DE19945140A1

    公开(公告)日：2001-04-12

    申请号：DE19945140

    申请日：1999-09-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： WEINRICH VOLKER ,  VEITH SEBASTIAN ,  HASLER BARBARA

    IPC: G03F7/40 ,  H01L21/033 ,  H01L21/308 ,  B32B15/08 ,  H01L21/312

    Abstract: The invention relates to a method for producing a mask layer having openings with reduced widths. An organic resist layer (3) is produced over the semiconductor substrate and is lithographically structured, whereby a resist opening (4) is produced in the resist layer (3). A polymer film (5) is deposited on the structured resist layer (3). Said film covers the side walls and the bottom (6) of the resist opening (4). The polymer film (5) is removed from the bottom (6) of the resist opening (4) by means of anisotropic etching.

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