公开(公告)号：JP2008234813A

公开(公告)日：2008-10-02

申请号：JP2007300593

申请日：2007-11-20

Applicant: Infineon Technologies Ag ,  Qimonda North America Corp ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト ,  キモンダ ノース アメリカ コーポレイション

Inventor： AUFINGER KLAUS ,  HAPP THOMAS ,  NIRSCHL THOMAS

IPC: G11C13/00 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L27/105 ,  H01L29/73 ,  H01L29/732 ,  H01L45/00

CPC classification number: H01L27/2445 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/79 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/148 ,  Y10T29/49002

Abstract: PROBLEM TO BE SOLVED: To increase density of a resistive memory composed of a phase transition material by reducing physical size while storing a multi-value of ternary or more. SOLUTION: The memory includes a first bipolar transistor, a first bit line, and a first resistive memory element coupled between a collector of the first bipolar transistor and the first bit line. The memory includes a second bit line, a second resistive memory element coupled between an emitter of the first bipolar transistor and the second bit line, and a word line coupled to a base of the first bipolar transistor. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：通过减少物理尺寸同时存储三元或更多的多值来增加由相变材料构成的电阻性存储器的密度。 存储器包括耦合在第一双极晶体管的集电极和第一位线之间的第一双极晶体管，第一位线和第一电阻存储元件。 存储器包括第二位线，耦合在第一双极晶体管的发射极和第二位线之间的第二电阻存储器元件，以及耦合到第一双极晶体管的基极的字线。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：DE102005053496A1

公开(公告)日：2007-05-10

申请号：DE102005053496

申请日：2005-11-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRUENING-VON SCHWERIN ULRIKE ,  HAPP THOMAS

IPC: G11C11/21 ,  G11C7/18 ,  G11C7/22 ,  G11C13/02 ,  H01L27/11

Abstract: The unit has a bit line (11), a ground line (12) and a set of memory cells (1), which are assigned to transistors (13), where the bit line and the ground line run parallel to each other. The transistors are arranged in an active area, which runs in sections angular to the bit and ground lines. The active area has two partial areas, which are electrically insulated from each other by an insulation-gate-area. An independent claim is also included for a method for operating a memory unit.

公开(公告)号：DE102005001460A1

公开(公告)日：2006-09-14

申请号：DE102005001460

申请日：2005-01-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS

IPC: H01L27/24

Abstract: The manufacturing method for a cell of a memory device entails the applying and structuring of an active material (2) on a backing substrate (1) for the forming of a rough component for the cell (14), and the introducing of impurities into the rough component in such a way that a concentration of the impurities in an edge region (15) is greater than in a core region (16) of the rough component in order to form from the rough component a cell which has a reduced specific electrical conductivity in the edge region. An independent claim is included for a memory device with a cell manufactured by the aforesaid method.

公开(公告)号：DE102004061548A1

公开(公告)日：2006-06-29

申请号：DE102004061548

申请日：2004-12-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PINNOW CAY-UWE ,  HAPP THOMAS ,  GRUENING-VON-SCHWERIN ULRIKE ,  ROEHR THOMAS

IPC: H01L27/24

Abstract: The memory cell matrix has the solid electrolyte memory cells which covers a layer pile (CC, R, PL), a word line (WL), a bit line (BL) and a plate line (PL) that are controlled by means of a selection transistor (T) and exhibits a common plate electrode (PL) which is connected to a common plate line. An independent claim is also included for: (a) manufacture of memory cell matrix; and (b) apparatus with a memory element.

公开(公告)号：DE102004041905A1

公开(公告)日：2006-03-02

申请号：DE102004041905

申请日：2004-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PINNOW CAY-UWE ,  HAPP THOMAS

IPC: C23C14/10 ,  H01L31/032 ,  H01L31/0392 ,  H01L31/18

Abstract: A chalcogenide layer includes a composition of compounds having the formula MmX1-m, where M denotes one or more elements selected from the group consisting of group IVb elements of the periodic system, group Vb elements of the periodic system and transition metals, X denotes one or more elements selected from the group consisting of S, Se and Te, and m has a value of between 0 and 1. The chalcogenide layer further includes an oxygen or nitrogen content in the range from 0.001 atomic % to 75 atomic %.

公开(公告)号：DE102004026002A1

公开(公告)日：2005-12-22

申请号：DE102004026002

申请日：2004-05-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PINNOW CAY-UWE ,  HAPP THOMAS

IPC: H01L21/8239 ,  H01L27/24 ,  H01L45/00

Abstract: The semiconductor assembly has solid electrolyte memory cell (4) arranged on a semiconductor substrate (1) such that it is parallel to the main surface (9) of the substrate. The cell has a reactive electrode (5) and an inert electrode (6) which are single-stage separated by solid electrolytes. The cell can be switched between high impedance and low impedance states. An independent claim is also included for the production method of the semiconductor assembly.

公开(公告)号：DE102004019862A1

公开(公告)日：2005-11-17

申请号：DE102004019862

申请日：2004-04-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS ,  PINNOW CAY-UWE

IPC: H01L21/283 ,  H01L21/768 ,  H01L27/24 ,  H01L45/00

Abstract: Sub-lithographic contact structure comprises an insulating layer (14) made from an insulating dielectric material with a through hole (15) arranged between a first contact electrode (10) and a second contact electrode (12), and a resistance changing layer (9) made from a material suitable having two states with different resistance values in response to selected energy pulses. The through hole has a tapered shape in a direction toward the first contact electrode so that the first contact region (17) has a sub-lithographic measurement in the first direction. An independent claim is also included for a contact structure.

公开(公告)号：DE102004003363A1

公开(公告)日：2005-08-18

申请号：DE102004003363

申请日：2004-01-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS ,  SYMANCZYK RALF

IPC: B82B1/00 ,  H01L21/28 ,  H01L21/8247 ,  H01L29/423

Abstract: In a process to manufacture a nano-storage component for storage of an electronic charge, a laminar substrate (101) is accorded a gate dielectric coating (102). Ions (104) are deposited at a predetermined depth within the dielectric layer by an ion beam (202). The resulting structure is heat treated, producing crystals within the dielectric material at the required depth.

公开(公告)号：DE10323414A1

公开(公告)日：2004-12-23

申请号：DE10323414

申请日：2003-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PINNOW CAY-UWE ,  MIKOLAJICK THOMAS ,  HAPP THOMAS ,  SYMANCZYK RALF

IPC: G11C11/34 ,  G11C13/02 ,  H01L45/00

Abstract: A solid-state electrolyte memory cell comprises a memory region (S) between anode (A) and cathode (K) on an ion-conductive material (I) having regions of different and controllable variable conductance (G). A barrier layer (B) between the ion-conductive and cathode layers suppresses a short, low-resistance error or hard write condition.

公开(公告)号：DE102004054558A1

公开(公告)日：2006-05-24

申请号：DE102004054558

申请日：2004-11-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HAPP THOMAS

IPC: H01L27/24

Abstract: The method involves structuring a hard mask (16), which is attached above upper electrode layer (12a) and switching active layer (13), into an elliptical or cylindrical form. A portion of the structured hard mask is back etched by isotropic etching. The upper electrode layer and the active layer are back etched by dry etching. An insulating layer made of an electrically insulating material is deposited on the hard mask. An independent claim is also included for a memory module comprising a memory cell with an additional contact for upper electrode.