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    Semiconductor memory having charge trap memory cell and its forming method
    1.
    发明专利
    Semiconductor memory having charge trap memory cell and its forming method 审中-公开
    具有充电陷阱存储单元的半导体存储器及其形成方法

    公开(公告)号：JP2006245579A

    公开(公告)日：2006-09-14

    申请号：JP2006051536

    申请日：2006-02-28

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： WILLER JOSEF ,  MIKOLAJICK THOMAS ,  LUDWIG CHRISTOPH ,  SCHULZE NORBERT ,  KUESTERS KARL HEINZ

    IPC: H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7923

    Abstract: PROBLEM TO BE SOLVED: To provide a memory having a charge trap memory cell, and a forming method of the memory having the trap memory cell.
    SOLUTION: The semiconductor memory is characterized in that a current direction of each channel region of a memory transistor is a longitudinal direction with respect to a related word line 3, in that a bit line 2 is arranged on a top surface of the word line so that it may be electrically insulated from the word line 3, in that a local interconnection 4, which is electrically conductive, of source/drain regions is prepared, in that the local interconnection 4 is arranged in a spacing zone between the above-mentioned word lines 3 so that it may be electrically insulated from the word line 3, and connected to the above-mentioned bit line 2 simultaneously, and in that a gate electrode is arranged within a trench at least partially formed inside a memory substrate.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：提供具有电荷陷阱存储单元的存储器，以及具有陷阱存储单元的存储器的形成方法。 解决方案：半导体存储器的特征在于，存储晶体管的每个沟道区域的电流方向是相对于相关字线3的纵向方向，因为位线2被布置在 字线，使得其可以与字线3电绝缘，因为制备了源/漏区的导电的局部互连4，其中局部互连4布置在上述之间的间隔区域中 所述字线3可以与字线3电绝缘，并且同时连接到上述位线2，并且栅极布置在至少部分地形成在存储器基板内部的沟槽内。 版权所有（C）2006，JPO＆NCIPI

    Multi-bit virtual ground nand memory device, and memory device
    2.
    发明专利
    Multi-bit virtual ground nand memory device, and memory device 审中-公开
    多位虚拟地址NAND存储器件和存储器件

    公开(公告)号：JP2006310868A

    公开(公告)日：2006-11-09

    申请号：JP2006127634

    申请日：2006-05-01

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： CORVIN LIAW ,  WILLER JOSEF ,  MIKOLAJICK THOMAS

    IPC: H01L21/8247 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC classification number: G11C16/0483 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11568

    Abstract: PROBLEM TO BE SOLVED: To provide a memory device capable of increasing storage density. SOLUTION: The array of charge-trapping multi-bit memory cells is arranged in a virtual-ground NAND architecture. The memory cells are erased by Fowler-Nordheim tunneling of electrons into the memory layers. The write operation is effected by hot electron hole pouring. A write voltage is applied by a bit line to two NAND chains in series. The subsequent bit line on the side of the memory cell to be programmed is maintained on floating potential, whereas the bit line on the other side is set to an inhibit voltage, which is provided to inhibit disturbance of a program in an addressed memory cell which is not to be programmed. This virtual-ground NAND architecture of charge-trapping memory cells enables an increased storage density. COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供能够增加存储密度的存储器件。 解决方案：电荷捕获多位存储单元的阵列被布置在虚拟地NAND架构中。 存储器单元被Fowler-Nordheim擦除，将电子隧穿到存储器层中。 写入操作通过热电子孔浇注来实现。 写入电压通过位线串联施加到两个NAND链。 要编程的存储器单元侧的后续位线保持浮置电位，而另一侧的位线被设置为禁止电压，其被设置为抑制寻址存储器单元中的程序的干扰， 不被编程 电荷俘获存储器单元的虚拟NAND架构能够提高存储密度。 版权所有（C）2007，JPO＆INPIT

    SEMICONDUCTOR MEMORY CELL AND METHOD FOR PRODUCING SAID CELL
    6.
    发明申请
    SEMICONDUCTOR MEMORY CELL AND METHOD FOR PRODUCING SAID CELL 审中-公开
    半导体存储单元和方法及其

    公开(公告)号：WO2004077574A3

    公开(公告)日：2004-11-18

    申请号：PCT/DE2004000365

    申请日：2004-02-27

    Applicant: INFINEON TECHNOLOGIES AG ,  PINNOW CAY-UWE ,  MIKOLAJICK THOMAS

    Inventor： PINNOW CAY-UWE ,  MIKOLAJICK THOMAS

    IPC: H01L21/28 ,  H01L21/336 ,  H01L29/78

    CPC classification number: H01L29/6684 ,  H01L21/28291 ,  H01L29/78391

    Abstract: The invention relates to a semiconductor memory cell and a method for producing said cell. According to said method, the capacity (CFe) of a ferroelectric capacitor assembly, which is formed by the contact and/or a region of an essentially constant potential between the gate isolation region (GOX) and a ferroelectric region (16), the ferroelectric region (16) and an upper gate electrode (18), is configured in a reduced manner relative to conventional conditions and/or relative to the capacity (CGOX) of a gate insulation capacitor assembly, which is formed by the border surface between a channel region (K) and the gate insulation region (GOX), the gate insulation region (GOX) and the contact and/or the region of an essentially constant potential between the gate isolation region (GOX) and the ferroelectric region (16).

    Abstract translation: 已提出了用于制备半导体存储器单元和方法，其中该电容由所述接触和/或一个Gateisolatiosbereich（GOX）之间实质上恒定电位的区域上形成的强电介质电容器布置的（CFE）和Ferroelektrikumsbereich（16 ），（该Ferroelektrikumsbereich 16）和上栅电极（18），相对于传统的条件和/或容量（相对CGOX）的栅极绝缘电容器布置，这是一个沟道区之间形成（从界面K）和栅极绝缘区（GOX）， 栅极绝缘区（GOX）和所述接触和/或Gateisolatiosbereich（GOX）和Ferroelektrikumsbereich（16）之间的大致恒定的电势的区域形成或减少。

    METHOD FOR PRODUCING FERROELECTRIC CAPACITORS AND INTEGRATED SEMICONDUCTOR MEMORY CHIPS
    8.
    发明申请
    METHOD FOR PRODUCING FERROELECTRIC CAPACITORS AND INTEGRATED SEMICONDUCTOR MEMORY CHIPS 审中-公开
    用于生产FERRO电气电容和集成半导体内存块

    公开(公告)号：WO02065518A3

    公开(公告)日：2002-11-21

    申请号：PCT/DE0104790

    申请日：2001-12-18

    Applicant: INFINEON TECHNOLOGIES AG ,  KASKO IGOR ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS

    Inventor： KASKO IGOR ,  KROENKE MATTHIAS ,  MIKOLAJICK THOMAS

    IPC: H01L27/105 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/115

    CPC classification number: H01L21/7687 ,  H01L21/76888 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

    Abstract: The invention relates to a method for the production of ferroelectric capacitors structured according to the stack principle, which are used in integrated semiconductor memory chips, wherein the individual capacitor modules (10, 11) have an oxygen barrier (4a, 4b) between a lower capacitor electrode (5a, 5b) and an electrically conductive plug (1a, 1b). At a site where it is not covered by the corresponding oxygen barrier (4a, 4b), an unstructured adhesive layer (3) is oxidized by the oxygen arising during the tempering process of the ferroelectric (6a, 6b) and forms insulating segments at said site in such a way that the lower capacitor electrodes (5a, 5b) of the ferroelectric capacitors (10, 11) are electrically insulated from one another. This makes it possible to eliminate the structuring step of the adhesive layer (3). Furthermore, said layer (3) serves as a getter of oxygen and inhibits the diffusion of oxygen to the plug.

    Abstract translation: 在用于生产在堆栈原则强电介质电容器建成为在集成的半导体存储器装置中使用的方法，所述个别电容器模块（10，11）具有氧阻隔（4A，4B）的下电容器电极之间（5A，5B）和导电插头（1A， 图1b）。 非结构化Hafschicht（3），在那里它们（4A，4B）是通过在铁电体的退火过程中的氧所覆盖的相应的氧屏障的不（6A，6B）形成，氧化的和形式的绝缘部分，使得下 电容器电极（图5a中，铁电电容器（10的​​5B9，11）彼此电绝缘。这消除了对粘接剂层（3），并且还，该层（3）可以被用于堵塞用于吸杂氧和抑制氧气扩散的图案化步骤。

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