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    Self-refresh circuit with optimized power consumption
    1.
    发明专利
    Self-refresh circuit with optimized power consumption 审中-公开
    具有优化消耗功率的自激电路

    公开(公告)号：JP2006309935A

    公开(公告)日：2006-11-09

    申请号：JP2006127846

    申请日：2006-05-01

    Applicant: Infineon Technologies Ag ,  インフィネオン テクノロジーズ アクチエンゲゼルシャフト

    Inventor： HOKENMAIER WOLFGANG

    IPC: G11C11/406

    CPC classification number: G11C11/406 ,  G11C2211/4061 ,  G11C2211/4067

    Abstract: PROBLEM TO BE SOLVED: To reduce power consumption in the hoiding mode of a DRAM as much as possible.
    SOLUTION: A random access memory device has a memory array, and a refresh rate generator circuit. The memory array has a plurality of memory cells that are configured to hold a charge. The memory array has an active mode and a standby mode. The refresh rate generator circuit is coupled to the memory array and coupled to generate a refresh signal having a rate. The refresh signal is used to periodically refresh the memory cells. The memory device detects when the memory array changes from its standby mode to its active mode and then increases the rate of the refresh signal when the memory array changes from its standby mode to its active mode.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：尽可能地降低DRAM的吸顶模式的功耗。 解决方案：随机存取存储器件具有存储器阵列和刷新率发生器电路。 存储器阵列具有被配置为保持电荷的多个存储器单元。 存储器阵列具有活动模式和待机模式。 刷新率发生器电路耦合到存储器阵列并被耦合以产生具有速率的刷新信号。 刷新信号用于周期性刷新存储单元。 存储器件检测存储器阵列何时从其待机模式改变到其活动模式，然后当存储器阵列从其待机模式改变到其激活模式时增加刷新信号的速率。 版权所有（C）2007，JPO＆INPIT

    RANDOM ACCESS MEMORY HAVING TEST CIRCUIT WITH TEST DATA COMPRESSION
    2.
    发明申请
    RANDOM ACCESS MEMORY HAVING TEST CIRCUIT WITH TEST DATA COMPRESSION 审中-公开
    具有测试数据压缩的测试电路的随机存取存储器

    公开(公告)号：WO2006063850A3

    公开(公告)日：2006-08-31

    申请号：PCT/EP2005013585

    申请日：2005-12-16

    Applicant: INFINEON TECHNOLOGIES AG ,  HOKENMAIER WOLFGANG

    Inventor： HOKENMAIER WOLFGANG

    IPC: G11C29/00

    CPC classification number: G11C29/40

    Abstract: A memory circuit comprises a memory and a first test circuit coupled to the memory. The first test circuit is configured to compare data read from memory cells with expected data for the memory cells to provide a first set of pass/fail signals for the memory cells, compress the first set of pass/fail signals for the memory cells into a second pass/fail signal, latch the second pass/fail signal in response to a data valid signal, maintain the latch of the second pass/fail signal if the second pass/fail signal indicates a failed test, combine the second pass/fail signal and a third pass/fail signal of a second test circuit to provide a fourth pass/fail signal, and pass the fourth pass/fail signal to a third test circuit.

    Abstract translation: 存储器电路包括存储器和耦合到存储器的第一测试电路。 第一测试电路被配置为将从存储器单元读取的数据与存储器单元的期望数据进行比较，以提供用于存储器单元的第一组通过/失败信号，将存储器单元的第一组通过/失败信号压缩为 第二通过/失败信号，响应于数据有效信号锁存第二通过/失败信号，如果第二通过/失败信号指示失败的测试，则保持第二通过/失败信号的锁存器，组合第二通过/失败信号 以及第二测试电路的第三通过/失败信号，以提供第四通过/失败信号，并将第四通过/失败信号传递给第三测试电路。

    3.
    发明专利
    未知

    公开(公告)号：DE10310081A1

    公开(公告)日：2003-09-25

    申请号：DE10310081

    申请日：2003-03-07

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： FIFIELD JOHN A ,  HOKENMAIER WOLFGANG

    IPC: H03K19/00 ,  H03K19/003

    Abstract: A multiple finger off chip driver (OCD) has a single level translator for each of a plurality of PFET fingers and NFET fingers which allow the impedance of the OCD to be varied to match the impedance of a driven load. A plurality of PFET and NFET finger selection devices are used to select various combinations of output FETS and ballast resistor finger combinations to drive an output signal at a desired impedance level. The ballast resistors are scaled in ohmic value to the size of the output finger it is connected to. In this configuration, a constant ratio of FET impedance to ballast resistance is maintained in each drive stage (finger). By selecting various combinations of fingers various driver impedances can be selected.

    4.
    发明专利
    未知

    公开(公告)号：DE112005003305T5

    公开(公告)日：2007-11-22

    申请号：DE112005003305

    申请日：2005-12-23

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HOKENMAIER WOLFGANG ,  VOGELSANG THOMAS ,  LORENZ HARALD

    IPC: G11C8/10 ,  G11C11/408

    Abstract: A memory circuit comprises a memory including a memory array, a twin cell mode predecoder, and a row address predecoder. The memory array comprises word lines. The twin cell mode predecoder is configured for selecting one of four word line activation configurations for the memory array. The four word line activation configurations include three twin cell word line activation configurations and a single cell word line activation configuration. The row address predecoder is configured for selecting one of four word lines if the single cell word line activation configuration is selected.

    6.
    发明专利
    未知

    公开(公告)号：DE10261327A1

    公开(公告)日：2003-08-07

    申请号：DE10261327

    申请日：2002-12-27

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： FRANKOWSKY GERD ,  HOKENMAIER WOLFGANG ,  HANSON DAVID R ,  LEHMANN GUNTHER

    IPC: G11C7/18 ,  G11C11/4097 ,  G11C29/00

    Abstract: A memory is provided having an array of rows and columns of memory cells. The memory includes plurality of sense amplifiers, each one having a true terminal and a compliment terminal. The memory also includes a plurality of pairs of twisted bit lines, each one of the pairs of lines being coupled to true and compliment terminals of a corresponding one of the plurality of sense amplifiers. A plurality of word lines is provided, each one being connected to a corresponding one of the rows of memory cells. An address logic section is fed by column address signals, fed to the bit lines, and row address signals, fed to the word lines, for producing invert/non-invert signals in accordance with the fed row and column address signals. The memory includes a plurality of inverters each one being coupled to a corresponding one of the sense amplifiers for inverting data fed to or read from the sense amplifier selectively in accordance with the invert/non-invert signals produced by the address logic.

    7.
    发明专利
    未知

    公开(公告)号：DE102005054898A1

    公开(公告)日：2006-06-01

    申请号：DE102005054898

    申请日：2005-11-17

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： FEKIH-ROMDHANE KHALED ,  HOKENMAIER WOLFGANG ,  HUMMLER KLAUS

    IPC: G11C29/18 ,  G06F12/00

    Abstract: A method of controlling an internal address counter which provides a count used in accessing a storage cell array to provide increased flexibility in the performance of a test on the array, comprising, rendering a normal overflow condition of the counter modified, thereby enabling alteration of the count provided by the counter in accordance with the requirements of the test being performed on the array.

    8.
    发明专利
    未知

    公开(公告)号：DE10356956A1

    公开(公告)日：2004-07-22

    申请号：DE10356956

    申请日：2003-12-05

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： HOKENMAIER WOLFGANG ,  NIERLE KLAUS ,  NORRIS ALAN D

    IPC: G11C29/48 ,  G11C29/00

    Abstract: A test operation of a memory array permits changing the test vector during the test by controlling the contents of a test vector through at least two external terminals not used during the test to change from a first to a second test vector, both of said first and second test vectors being stored in a controllable register connected to the external terminals.

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