公开(公告)号：WO2004079815A3

公开(公告)日：2004-12-02

申请号：PCT/EP2004001768

申请日：2004-02-23

Applicant: INFINEON TECHNOLOGIES AG ,  CASAROTTO DANIELE ,  HUMMLER KLAUS

Inventor： CASAROTTO DANIELE ,  HUMMLER KLAUS

IPC: H01L21/336 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC classification number: H01L29/66825 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11556 ,  H01L29/42336 ,  H01L29/7883

Abstract: A non-volatile memory cell which can be easily integrated into processes for forming DRAM cells using trench capacitors is disclosed. The non-volatile memory cell comprises a transistor formed in a trench created below the top surface of the substrate. The transistor includes a U-shaped floating gate which lines the trench. A dielectric layer surrounds the floating gate, isolating it from the trench sidewalls and bottom as well as a control gate located in the inner trench formed by the floating gate. A buried diffusion region abuts the bottom of the floating gate. First and second diffusion regions are located on first and second sides of the trench. The first diffusion region is on the surface of the substrate while the second diffusion region extends from the surface and couples to the buried diffusion region. A wordline is coupled to the control gate.

Abstract translation: 公开了一种易于集成到使用沟槽电容器形成DRAM单元的工艺中的非易失性存储单元。 非易失性存储单元包括形成在衬底的顶表面下方形成的沟槽中的晶体管。 晶体管包括对沟槽进行排列的U形浮动栅极。 电介质层围绕浮动栅极，将其与沟槽侧壁和底部隔离，以及位于由浮动栅极形成的内部沟槽中的控制栅极。 掩埋扩散区域邻接浮动栅极的底部。 第一和第二扩散区位于沟槽的第一和第二侧上。 第一扩散区位于衬底的表面上，而第二扩散区从表面延伸并耦合到掩埋扩散区。 字线耦合到控制门。

公开(公告)号：DE69736999D1

公开(公告)日：2007-01-11

申请号：DE69736999

申请日：1997-03-19

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： LEVINE ERNEST ,  ARNOLD NORBERT ,  HUMMLER KLAUS ,  WEILAND RAINER

IPC: G01B11/00 ,  H01L21/66 ,  G01B15/00 ,  G01Q20/02 ,  G01Q30/02 ,  H01J37/304 ,  H01L21/027

Abstract: A method is disclosed for locating a particular small objects (down to submicron) within an array of periodically arranged like objects utilizing a scanning tool. The method includes scanning the array for generating a plurality of pulses, which correspond to these objects contained within the array. Counting the plurality of pulses in order to locate the particular object within the array.

公开(公告)号：DE10353771A1

公开(公告)日：2004-06-17

申请号：DE10353771

申请日：2003-11-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HUMMLER KLAUS

IPC: H01L21/334 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/108

公开(公告)号：DE10317601A1

公开(公告)日：2003-12-04

申请号：DE10317601

申请日：2003-04-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HUMMLER KLAUS ,  SCHOLZ ARND

IPC: H01L21/20 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: A trench top isolation (TTI) layer (148) and method of forming thereof for a vertical DRAM. A first assist layer (134) is disposed over trench sidewalls (133) and trench capacitor top surfaces (131). A second assist layer (136) is disposed over the first assist layer (134). The second assist layer (136) is removed from over the trench capacitor top surface (131), and the first assist layer (134) is removed from the trench capacitor top surface (131) using the second assist layer (136) as a mask. The second assist layer (136) is removed, and a first insulating layer (140) is disposed over the first assist layer (134) and trench capacitor top surface (131). A second insulating layer (142) is disposed over the first insulating layer (140), and the second insulating layer (142) is removed from the trench sidewalls (133). The first insulating layer (140) and the first assist layer (134) are removed from the trench sidewalls (133). The TTI layer (148) comprises the first and second insulating layer portions (146/144) that are left remaining over the trench capacitors (118). The TTI layer (148) has a greater thickness over the trench capacitor inner regions (152) than over the trench capacitor outer regions (150).

公开(公告)号：DE10324053A1

公开(公告)日：2003-12-18

申请号：DE10324053

申请日：2003-05-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HUMMLER KLAUS

IPC: H01L21/762 ,  H01L21/8242 ,  H01L27/108

公开(公告)号：DE10317601B4

公开(公告)日：2008-04-03

申请号：DE10317601

申请日：2003-04-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HUMMLER KLAUS ,  SCHOLZ ARND

IPC: H01L21/8242 ,  H01L21/20 ,  H01L21/334 ,  H01L27/108

Abstract: A trench top isolation (TTI) layer (148) and method of forming thereof for a vertical DRAM. A first assist layer (134) is disposed over trench sidewalls (133) and trench capacitor top surfaces (131). A second assist layer (136) is disposed over the first assist layer (134). The second assist layer (136) is removed from over the trench capacitor top surface (131), and the first assist layer (134) is removed from the trench capacitor top surface (131) using the second assist layer (136) as a mask. The second assist layer (136) is removed, and a first insulating layer (140) is disposed over the first assist layer (134) and trench capacitor top surface (131). A second insulating layer (142) is disposed over the first insulating layer (140), and the second insulating layer (142) is removed from the trench sidewalls (133). The first insulating layer (140) and the first assist layer (134) are removed from the trench sidewalls (133). The TTI layer (148) comprises the first and second insulating layer portions (146/144) that are left remaining over the trench capacitors (118). The TTI layer (148) has a greater thickness over the trench capacitor inner regions (152) than over the trench capacitor outer regions (150).

公开(公告)号：DE10302117B4

公开(公告)日：2007-10-25

申请号：DE10302117

申请日：2003-01-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HUMMLER KLAUS

IPC: H01L21/8242 ,  H01L21/336 ,  H01L27/108

Abstract: A vertical gate transistor has a gate stud (14) that extends above the substrate (20) surface in order to contact a word line. The stud is formed of a first material (26) and a second material (28) having differently selective etch characteristics. The second material (18) is formed within a recess in the first material (26), and the first material (26) is then selectively etched back substantially, with the second material remaining and extending above the surrounding substrate. The gate stud (14) can then accommodate a thick array top oxide (34) and subsequent chemical mechanical polish and perform in a wide process window.

公开(公告)号：DE102005054898A1

公开(公告)日：2006-06-01

申请号：DE102005054898

申请日：2005-11-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEKIH-ROMDHANE KHALED ,  HOKENMAIER WOLFGANG ,  HUMMLER KLAUS

IPC: G11C29/18 ,  G06F12/00

Abstract: A method of controlling an internal address counter which provides a count used in accessing a storage cell array to provide increased flexibility in the performance of a test on the array, comprising, rendering a normal overflow condition of the counter modified, thereby enabling alteration of the count provided by the counter in accordance with the requirements of the test being performed on the array.

公开(公告)号：DE10336481A1

公开(公告)日：2004-03-18

申请号：DE10336481

申请日：2003-08-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHOLZ ARND ,  HUMMLER KLAUS

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/108

公开(公告)号：DE10324585A1

公开(公告)日：2003-12-18

申请号：DE10324585

申请日：2003-05-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HUMMLER KLAUS

IPC: H01L21/8242 ,  H01L21/336

Abstract: The present invention provides an easy post GC etch treatment that can remove vertical GC residues without affecting the support devices while ensuring a robust GC to vertical gate contact in all alignment scenarios. The conductive vertical gate contact of the present invention, in conjunction with any DT top isolation approach, allows for an aggressive post GC etch treatment to avoid gate to bit line shorts without compromising the contact between the GC and the vertical gate.