公开(公告)号：DE10345466A1

公开(公告)日：2005-04-28

申请号：DE10345466

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRUSS STEFAN ,  FROEHLICH HANS-GEORG ,  BAUCH LOTHAR ,  TEIPEL ANSGAR

IPC: G03B27/32 ,  G03F9/00 ,  H01L21/66

公开(公告)号：DE10345524A1

公开(公告)日：2005-05-04

申请号：DE10345524

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEIPEL ANSGAR ,  GRUSS STEFAN ,  FROEHLICH HANS-GEORG

IPC: H01L23/544 ,  H01L21/66 ,  G01B15/00 ,  G03F7/20

Abstract: The method involves forming a structure with structural components within a first range of a layer of a substrate of the semiconductor wafer by means of photolithographic projection. The components of the structure are for circuit samples. A reference structure is formed by photolithographic projection where the reference structure is trained in such a way, that it encloses the first range. A second structure with structural components within a second range is provided by photolithographic projection, where the structural components have a reference structure partly surrounding the second range. A distance is measured between the first structural component and the reference structure by a scanning electron microscope, in order to determine first placing error. A second distance is measured between one of the second structural components and the reference structure by a scanning electron microscope. A misalignment of the first structural component to the second structural components is calculated from the placing errors. An independent claim is included for an overlay measuring structure for the determination of a relative misalignment of two structured circuit samples on a semiconductor wafer.

公开(公告)号：DE102004015930A1

公开(公告)日：2005-11-03

申请号：DE102004015930

申请日：2004-03-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： JAHNKE ANDREAS ,  HENKE WOLFGANG ,  KUNKEL GERHARD ,  TEIPEL ANSGAR ,  IACONO STEPHANIE

IPC: G03F7/20

Abstract: The method involves applying a photoresist layer (10) on top of a semiconductor wafer (5). A projection apparatus is operated in two modes to project a circuit path pattern (14) onto the layer, where exposure light intensity is selected to be above an exposure threshold of the layer in one mode. The phase of the exposure light is controlled by an alternating phase shift mask (12). The layer is processed to form a resist pattern. An independent claim is also included for a use of a lithographic projection method for fabrication of an integrated circuit.

公开(公告)号：DE102004063522A1

公开(公告)日：2006-03-23

申请号：DE102004063522

申请日：2004-12-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FROEHLICH HANS-GEORG ,  TEIPEL ANSGAR ,  VORWERK MANUEL

IPC: G03F9/00 ,  G03F7/22

Abstract: A method for correcting structure-size-dependent positioning errors during the photolithographic projection by an exposure apparatus and the use thereof includes providing an exposure apparatus for exposing a plurality of exposure fields and a simulation model of the exposure apparatus for specifying correction values for intra-field errors, providing a first pattern with first structure elements and first measurement marks, which, in the case of a projection, are beset by a first positioning error and a second positioning error dependent on the dimensions and the position in the exposure field, providing a correction function suitable for specifying the first and the second positioning error, determining an average relative positioning error including the first and the second positioning error, calculating correction values for the control of the exposure apparatus, and transmitting the correction values to the exposure apparatus so that subsequent exposures are performed with an improved overlay.

公开(公告)号：DE10345524B4

公开(公告)日：2005-10-13

申请号：DE10345524

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TEIPEL ANSGAR ,  GRUSS STEFAN ,  FROEHLICH HANS-GEORG

IPC: H01L23/544 ,  H01L21/66 ,  G01B15/00 ,  G03F7/20