公开(公告)号：DE102005007280A1

公开(公告)日：2006-11-02

申请号：DE102005007280

申请日：2005-02-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRUSS STEFAN ,  BAUCH LOTHAR

IPC: H01L23/544 ,  G03F7/00 ,  G03F9/00

Abstract: The process involves forming a test mark for the laterally structured layer on a substrate, in which the test mark is provided with a layer surface with first and second edges and a layer-free substrate with third and fourth edges. The center (M1) between the first and fourth edges and the center (M2) between the second and third edges are then determined after seizing the test mark. The distance between the determined centers is then measured as the critical dimension of the laterally structured layer. The layer surface with the first and second edges borders the layer-free regions of the substrate. The layer-free surface with the third and fourth edges borders on the regions of the substrate where the laterally structured layer is formed. The first, second, third and fourth edges are arranged in parallel and next to each other. Independent claims are included for the following: (1) a lithography mask used in fabrication of he laterally structured layer on a substrate; and (2) a test mark.

公开(公告)号：DE102005018737A1

公开(公告)日：2006-10-26

申请号：DE102005018737

申请日：2005-04-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VOELKEL LARS ,  BAUCH LOTHAR ,  KLINGBEIL PATRICK ,  HERPE JOACHIM ,  VOGT MIRKO

IPC: G03F7/09 ,  G03F7/00 ,  H01L21/31

Abstract: The method involves providing semiconductor wafers with a structured layer/layer stack, and applying an organic anti-reflection layer (41) on the layer/layer stack. A photoresist layer (1) is applied on the anti-reflection layer, and the photoresist layer is exposed in sections by an imaging device and a photomask. The photoresist layer is processed, where a structure of the photomask is formed as an opening in the photoresist layer.

公开(公告)号：DE10203358A1

公开(公告)日：2003-04-03

申请号：DE10203358

申请日：2002-01-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KUNKEL GERHARD ,  SACHSE HERMANN ,  BAUCH LOTHAR ,  WURZER HELMUT

IPC: G03F1/32 ,  G03F1/00 ,  G03F1/38 ,  G03F1/14

公开(公告)号：DE10000004A1

公开(公告)日：2001-05-17

申请号：DE10000004

申请日：2000-01-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEIBERG WOLFGANG ,  BAUCH LOTHAR ,  GRANDREMY GREGOIRE ,  STEINBACH ANDREAS ,  BRASE GABRIELA

IPC: H01L21/768 ,  H01L21/283

Abstract: Production of conducting pathways comprises applying a metal layer (1) to a substrate with integrated circuits; applying an insulating layer (2) to the metal layer; producing a TiN layer (3) and subsequently a photoresist layer (5); producing a first resist mask by forming a first hole pattern in the photoresist layer; removing the TiN layer exposed in openings (6) and the insulating layer underneath; removing the photoresist layer and the TiN layer; and depositing metal in the trenches and contact holes. An Independent claim is also included for a process for the production of the conducting pathways. Preferred Features: An anitreflection layer formed by a SION layer (4) is arranged between the photoresist layer and the TiN layer. The TiN layer is applied using a reactive plasma sputtering process.

公开(公告)号：DE19939852B4

公开(公告)日：2006-01-12

申请号：DE19939852

申请日：1999-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BAUCH LOTHAR ,  ZELL THOMAS ,  LEHR MATTHIAS UWE ,  KIESLICH ALBRECHT

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: In the fabrication of stacked vias, metal islands referred to as landing pads are introduced for the purpose of contact-connection between the vias that are arranged one above the other. The metal islands project laterally beyond the vias to a significant extent on account of the line shortening effect. The vias arranged in layers lying one above the other are laterally offset with respect to one another. The landing pad of the invention is configured as an interconnect running between the vias. On account of the line shortening effect, which is less critical for longer tracks, contact areas provided at the ends of the interconnect do not have to be chosen to be as large as the square contact areas of conventional metal islands and can therefore be accommodated to save more space on a circuit layout to be miniaturized. The shrink factor of such a semiconductor structure is increased.

公开(公告)号：DE10361875A1

公开(公告)日：2005-07-21

申请号：DE10361875

申请日：2003-12-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFORR RAINER ,  MUELDERS THOMAS ,  CRELL CHRISTIAN ,  BAUCH LOTHAR ,  ZIEBOLD RALF ,  MOELLER HOLGER ,  GRAESER ANNETT

IPC: G03F1/00 ,  G03F1/36 ,  G03F1/14 ,  G03F1/08

Abstract: A lithography mask comprises a structure for transferring a layout onto a substrate. A blind macrostructure (1) is used to suppress scattered light, and is located at a bright region of the structure. The macrostructure is partially transparent and does not print on the substrate or form a resist structure.

公开(公告)号：DE102005052046A1

公开(公告)日：2007-05-03

申请号：DE102005052046

申请日：2005-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NEES DIETER ,  BAUCH LOTHAR ,  GEYER STEFAN ,  BRUCH JENS UWE ,  KLINGBEIL PATRICK ,  SCHUMACHER KARL ,  STAECKER JENS ,  SCHIWON ROBERTO ,  HOMMEN HEIKO ,  BONNESS ANJA

IPC: G03F1/64

Abstract: A lithographic projection photo-mask (5) comprises: (a) a transparent substrate (10) with a pattern (14) of structural elements (16); (b) a frame (18), on the substrate outside the pattern; (c) a protective film (20) above the substrate, forming an enclosed volume filled with purging gas; and (d) an arrangement (32) of absorber within the enclosed volume, to remove harmful materials from the gas and inhibit crystal formation on the mask. A photo-mask (5) for lithographic projection comprises: (a) a transparent substrate (10), provided on its front with a pattern (14) of absorbing, partially absorbing or phase-shifting structural elements (16); (b) a frame (18), located on the front side of the substrate outside the pattern; (c) a protective film (20), located above the substrate on the frame, forming an enclosed volume filled with purging gas; and (d) an absorber arrangement (32), including absorber located in the frame region within the enclosed volume, for removing harmful materials from the purging gas to inhibit crystal formation on the mask. An independent claim is included for a method for using the mask in an exposure plant, involving: (A) supplying the mask into an exposure device from a protective container; (B) carrying out one or more exposure processes in the exposure device using light from an ultraviolet source; and (C) withdrawing the mask from the exposure device into the protective container.

公开(公告)号：DE10345466A1

公开(公告)日：2005-04-28

申请号：DE10345466

申请日：2003-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GRUSS STEFAN ,  FROEHLICH HANS-GEORG ,  BAUCH LOTHAR ,  TEIPEL ANSGAR

IPC: G03B27/32 ,  G03F9/00 ,  H01L21/66

公开(公告)号：DE10054969A1

公开(公告)日：2002-03-28

申请号：DE10054969

申请日：2000-11-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEIBERG WOLFGANG ,  BAUCH LOTHAR ,  LEHR MATTHIAS UWE

IPC: C23F4/00 ,  H01L21/311 ,  H01L21/314 ,  H01L21/3213

Abstract: Structuring metal layers by lithography, especially i-line lithography or DIN lithography and subsequent plasma etching, especially reactive ion etching, comprises applying the required antireflection layer (3) as a dielectric layer before the reactive ion etching of the uppermost metal layer of several metal layers placed on top of each other. Preferred Features: The thickness of the dielectric antireflection layer is chosen so that the light used in the lithographic process undergoes minimal reflection. The dielectric antireflection layer forms a highly selective etching mask in combination with a thin photoresist layer (4). The antireflection layer comprises silicon oxy nitride.

公开(公告)号：DE19945425A1

公开(公告)日：2001-04-19

申请号：DE19945425

申请日：1999-09-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEIBERG WOLFGANG ,  BAUCH LOTHAR ,  LEHR MATTHIAS UWE ,  LUEKEN ELKE ,  MOLL PETER ,  VOGT MIRKO ,  KIESLICH ALBRECHT

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/321 ,  G03F7/20

Abstract: Structuring a metal layer (M) during semiconductor finishing comprises applying a lacquer layer (L) to a semiconductor substrate; structuring the lacquer layer using lithography and producing an etching mask; and structuring the metal layer using the mask. Initially a hard mask is applied to the metal layer and the lacquer layer is applied to the mask, where the lacquer layer is thin so that only the mask and not the metal layer can be structured with the aid of the lacquer layer. The hard mask is structured to form an etching mask with the aid of the structured lacquer layer. The metal layer is structured with the hard mask as an etching mask. Preferred Features: The hard mask has a first layer (H1) of an oxide, preferably silicon dioxide, and a second layer (H2) to reduce reflection and made of silicon nitride. The metal layer is made of aluminum and/or copper.