公开(公告)号：WO0225730A8

公开(公告)日：2002-12-27

申请号：PCT/US0142263

申请日：2001-09-24

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KUNKEL GERHARD ,  BUTT SHAHID ,  DIVAKARUNI RAMACHANDRAN ,  REITH ARMIN M ,  NAEEM MUNIR D

IPC: H01L21/8242

CPC classification number: H01L27/10864 ,  H01L27/1087 ,  H01L27/10891

Abstract: A method of forming a trench can be used in the fabrication of dynamic random access memory (DRAM) cells. In one aspect, a first layer of a first material (e.g., polysilicon) (104) is formed over a semiconductor region (e.g., a silicon substrate) (100). The first layer is patterned to remove portions of the first material. A second material (e.g., oxide) (112, 120) can then be deposited to fill the portions where the first material was removed. After removing the remaining portions of the first layer of first material, a trench (122) can be etched in the semiconductor region. The trench would be substantially aligned to the second material.

Abstract translation: 形成沟槽的方法可用于制造动态随机存取存储器（DRAM）单元。 在一个方面，在半导体区域（例如，硅衬底）（100）上形成第一材料（例如，多晶硅）（104）的第一层。 图案化第一层以去除第一材料的部分。 然后可以沉积第二材料（例如氧化物）（112,120）以填充去除第一材料的部分。 在去除第一材料的第一层的剩余部分之后，可以在半导体区域中蚀刻沟槽（122）。 沟槽将基本上对准第二材料。

公开(公告)号：WO0137320A3

公开(公告)日：2001-12-06

申请号：PCT/US0030404

申请日：2000-11-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： REITH ARMIN M ,  HSU LOUIS ,  HAFFNER HENNING ,  LEHMANN GUNTHER

IPC: G06F17/50 ,  H01L21/02 ,  H01L21/82 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

CPC classification number: H01L28/40 ,  H01L27/10861 ,  H01L27/10894 ,  H01L27/10897

Abstract: A method to optimize the size and filling of decoupling capacitors for very large scale integrated circuits (VLSI) using existing lithographic fillers. The method combines the automatic or manual generation of lithographic fill patterns with the forming of the capacitors. According to the method, when the chip layout is about to be finished, all remaining empty space on the chip gets identified by a layout tool. Then, the closest power-supply nets get extracted. All power supplies and their combinations are sorted in a connection table which determines the appropriate types of capacitances once the power-supply nets closest to the empty spaces extracted from the layout. The empty spaces are then assigned appropriate decoupling capacitances. Decoupling capacitors generated by the method are suitable for VLSI power supplies for noise reduction.

Abstract translation: 使用现有的平版印刷填料，优化大型集成电路（VLSI）的去耦电容的尺寸和填充的方法。 该方法将自动或手动生成光刻填充图案与电容器的形成相结合。 根据该方法，当芯片布局即将完成时，芯片上剩余的空余空间由布局工具识别。 然后，最近的电源网络被提取。 所有电源及其组合在连接表中排序，一旦电源网最接近从布局提取的空白空间中，则确定适当类型的电容。 然后空的空间被分配适当的去耦电容。 通过该方法产生的去耦电容适用于降低噪声的VLSI电源。

公开(公告)号：WO0225730A3

公开(公告)日：2002-10-24

申请号：PCT/US0142263

申请日：2001-09-24

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KUNKEL GERHARD ,  BUTT SHAHID ,  DIVAKARUNI RAMACHANDRAN ,  REITH ARMIN M ,  NAEEM MUNIR D

IPC: H01L21/8242

CPC classification number: H01L27/10864 ,  H01L27/1087 ,  H01L27/10891

Abstract: A method of forming a trench can be used in the fabrication of dynamic random access memory (DRAM) cells. In one aspect, a first layer of a first material (e.g., polysilicon) (104) is formed over a semiconductor region (e.g., a silicon substrate) (100). The first layer is patterned to remove portions of the first material. A second material (e.g., oxide) (112, 120) can then be deposited to fill the portions where the first material was removed. After removing the remaining portions of the first layer of first material, a trench (122) can be etched in the semiconductor region. The trench would be substantially aligned to the second material.

Abstract translation: 可以在制造动态随机存取存储器（DRAM）单元中使用形成沟槽的方法。 在一个方面，第一材料（例如，多晶硅）（104）的第一层形成在半导体区域（例如，硅衬底）（100）之上。 第一层被图案化以去除第一材料的一部分。 然后可以沉积第二材料（例如氧化物）（112,120）以填充第一材料被去除的部分。 在去除第一层第一材料的剩余部分之后，可以在半导体区中蚀刻沟槽（122）。 沟槽将基本上与第二材料对齐。

公开(公告)号：WO0199160A3

公开(公告)日：2002-10-17

申请号：PCT/US0119684

申请日：2001-06-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： SCHNABEL RAINER FLORIAN ,  RADENS CARL J ,  LANDIS HOWARD ,  PARK YOUNG JIN ,  KOTECKI DAVID ,  REITH ARMIN M ,  TRICKLE WAYNE ,  WORDEMAN MATTHEW R

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10808

Abstract: A semiconductor memory device (100), in accordance with the present invention, includes a substrate having a major surface including an array region (102) and a support region (104). The array region includes memory cell structures (106) having a first height above the major surface of the substrate. The support area includes dummy structures (119) formed therein having a second height above the major surface. A dielectric layer (118) is formed over the memory cell structures in the array region and the dummy structures in the support region such that a top surface (122) of the dielectric layer is substantially planar wherein topographical features are substantially eliminated on the dielectric layer across the array region and the support region.

Abstract translation: 根据本发明的半导体存储器件（100）包括具有包括阵列区域（102）和支撑区域（104）的主表面的衬底。 阵列区域包括在衬底的主表面上方具有第一高度的存储单元结构（106）。 支撑区域包括形成在其中的在主表面上方具有第二高度的虚拟结构（119）。 在阵列区域中的存储单元结构和支撑区域中的虚拟结构之间形成电介质层（118），使得电介质层的顶表面（122）基本上是平面的，其中在介电层上基本上消除了形貌特征 跨越阵列区域和支撑区域。