公开(公告)号：WO0199160A3

公开(公告)日：2002-10-17

申请号：PCT/US0119684

申请日：2001-06-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： SCHNABEL RAINER FLORIAN ,  RADENS CARL J ,  LANDIS HOWARD ,  PARK YOUNG JIN ,  KOTECKI DAVID ,  REITH ARMIN M ,  TRICKLE WAYNE ,  WORDEMAN MATTHEW R

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10808

Abstract: A semiconductor memory device (100), in accordance with the present invention, includes a substrate having a major surface including an array region (102) and a support region (104). The array region includes memory cell structures (106) having a first height above the major surface of the substrate. The support area includes dummy structures (119) formed therein having a second height above the major surface. A dielectric layer (118) is formed over the memory cell structures in the array region and the dummy structures in the support region such that a top surface (122) of the dielectric layer is substantially planar wherein topographical features are substantially eliminated on the dielectric layer across the array region and the support region.

Abstract translation: 根据本发明的半导体存储器件（100）包括具有包括阵列区域（102）和支撑区域（104）的主表面的衬底。 阵列区域包括在衬底的主表面上方具有第一高度的存储单元结构（106）。 支撑区域包括形成在其中的在主表面上方具有第二高度的虚拟结构（119）。 在阵列区域中的存储单元结构和支撑区域中的虚拟结构之间形成电介质层（118），使得电介质层的顶表面（122）基本上是平面的，其中在介电层上基本上消除了形貌特征 跨越阵列区域和支撑区域。

公开(公告)号：WO0203423A3

公开(公告)日：2002-08-08

申请号：PCT/US0121164

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUNKEL GERHARD ,  HSU LOUIS L ,  LEE HEON ,  KOTECKI DAVID ,  LIMB YOUNG ,  RADENS CARL J ,  PARK YOUNG JIN

IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/10852 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts (28) because the stacked capacitors (46,48,50) are co-planar with the bit lines (36) and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

Abstract translation: 提供了一种DRAM单元和制造方法，其通过将堆叠的电容器形成与电触点并入来消除关键的光刻制造步骤。 由于层叠的电容器（46,48,50）与位线（36）是共面的，所以单个光刻步骤可用于形成电触点（28），并且堆叠的电容器位于设置在 位线。 与常规的电容器位线（COB）DRAM单元不同，这种位线旁边的DRAM电池消除了将触点专用于电容器的需要，使得可以在较低的全局地形下实现更高的电容。

公开(公告)号：WO0199186A3

公开(公告)日：2002-10-10

申请号：PCT/US0119658

申请日：2001-06-20

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KUNKEL GERHARD ,  KOTECKI DAVID ,  PARK YOUNG JIN ,  GUTMANN ALOIS ,  MANDELMAN JACK A

IPC: H01L21/761 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/761

Abstract: A semiconductor device, in accordance with the present invention, includes a doped semiconductor substrate (102) wherein the doping of the substrate has a first conductivity and a device region (110) formed near a surface of the substrate. The device region includes at least one device well. A buried well (104) is formed in the substrate below the device region. The buried well is doped with dopants having a second conductivity. A trench region (124) surrounds the device region and extends below the surface of the substrate to at least the buried well such that the device region is isolated from other portions of the substrate by the buried well and the trench region.

Abstract translation: 根据本发明的半导体器件包括其中衬底的掺杂具有第一导电性的掺杂半导体衬底（102）和形成在衬底的表面附近的器件区（110）。 器件区域包括至少一个器件。 掩埋阱（104）形成在器件区域下方的衬底中。 掩埋阱掺杂具有第二导电性的掺杂剂。 沟槽区域（124）围绕器件区域并且在衬底的表面下方延伸到至少掩埋阱，使得器件区域通过掩埋阱和沟槽区域与衬底的其他部分隔离。

公开(公告)号：WO0203423A8

公开(公告)日：2002-04-11

申请号：PCT/US0121164

申请日：2001-07-02

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KUNKEL GERHARD ,  HSU LOUIS L ,  LEE HEON ,  KOTECKI DAVID ,  LIMB YOUNG ,  RADENS CARL J ,  PARK YOUNG JIN

IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532 ,  H01L

CPC classification number: H01L27/10852 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts because the stacked capacitors are co-planar with the bit lines and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

Abstract translation: 提供DRAM单元和制造方法，其通过将堆叠的电容器结构与电触点合并来消除关键的光刻制造步骤。 因为堆叠的电容器与位线共面并且堆叠的电容器位于位线之间提供的绝缘材料中，所以可以使用单个光刻步骤来形成电触点。 与传统的电容器位线（COB）DRAM单元不同，这种位于电容器旁边的位线DRAM单元消除了对电容器专用接触的需要，使得可以用较低的全局地形实现更高的电容。

公开(公告)号：JP2000058795A

公开(公告)日：2000-02-25

申请号：JP21248499

申请日：1999-07-27

Applicant: SIEMENS AG ,  IBM

Inventor： SHEN HUA ,  NUETZEL JOACHIM ,  RADENS CARL J ,  KOTECKI DAVID

IPC: H01G4/12 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To maintain an appropriate height of a lower part electrode while the surface region of the lower part electrode for a stacked capacity is improved, by forming a first electrode electrically combined to a conductive access path and then forming a second electrode on a dialectics layer formed on the first electrode. SOLUTION: A tapered surface 122 in a trench 116 is formed as a conical part in the trench 116. A lower part electrode (first electrode) 124 is formed on the upper surface comprising a side wall 118 (and the tapered surface 122) by deposition of a metal layer 126, for example, such noble metal as platinum (Pt). A high dielectric constant layer 134 is formed on the metal layer 126. The metal layer 126 forms a lower part electrode of a stacked capacitor. An upper part electrode (second electrode) 136 is formed by deposition of a conductive material above the high dielectric constant layer 134 in the trench 116. The upper part electrode 136 is prefered to be formed of platinum, while such a conductive material as iridium(Ir), for example, may be used.