公开(公告)号：US09744624B2

公开(公告)日：2017-08-29

申请号：US14742070

申请日：2015-06-17

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Jaen-Don Lan ,  Pin-Chung Lin ,  Chen-Rui Tseng ,  Cheng-En Ho ,  Yu-An Chen

IPC: H05K3/46 ,  B23K26/402 ,  H05K3/42 ,  B23K26/382 ,  B23K103/00

CPC classification number: B23K26/402 ,  B23K26/382 ,  B23K26/389 ,  B23K2101/40 ,  B23K2103/172 ,  B23K2103/30 ,  B23K2103/42 ,  B23K2103/50 ,  H05K3/426 ,  H05K3/4644 ,  H05K2201/0341

Abstract: Disclosed is a method for manufacturing a circuit board, including preparing a substrate having a resin layer and a stop layer, forming at least one conduction hole penetrating the resin layer and stopping at the stop layer, forming a first metal layer through a sputtering process, forming a second metal layer on the first metal layer through a chemical plating process, forming a third metal layer having a circuit pattern, exposing part of the second metal layer and filling up the conduction hole through an electroplating process, and etching the second metal layer and the first metal layer under the second metal layer to expose the resin layer under the first metal layer. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and stable. The etched circuit pattern has a line width/pitch less than 10 μm for fine line width/pitch.

公开(公告)号：US09439292B1

公开(公告)日：2016-09-06

申请号：US14641016

申请日：2015-03-06

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yi-Fan Kao ,  Jaen-Don Lan ,  Yung-Lin Chia ,  An-Ping Tseng

IPC: H05K1/18 ,  H05K3/06 ,  H05K3/00

CPC classification number: H05K3/064 ,  H01L23/5389 ,  H05K1/185 ,  H05K1/188 ,  H05K3/0008 ,  H05K3/108 ,  H05K3/305 ,  H05K3/425 ,  H05K2201/09563 ,  H05K2201/10674 ,  H05K2203/166

Abstract: A method for manufacturing a circuit board with a buried element having high density pin count, wherein a micro copper window formed in a first circuit by patterned dry film electroplating is easily controlled less than 50 μm so that the micro conduction holes formed after the laser drilling each has a diameter greatly shrunk less than 50 μm so as to highly increase density of the micro conduction holes, thereby facilitating in burial of the buried element with the high density pin count. Additionally, by disposing the micro conduction holes in the same elevation, optically aligning a fixing position for the buried element can be controlled precisely.

Abstract translation: 一种制造具有高密度引脚数的埋入元件的电路板的方法，其中通过图案化干电镀电镀形成在第一电路中的微铜窗容易控制在小于50μm，从而在激光钻孔之后形成的微导电孔 每个具有大大缩小到小于50μm的直径，从而高度增加微通孔的密度，从而便于以高密度引脚数掩埋埋入元件。 此外，通过将相同高度的微通孔设置在一起，可精确地控制掩埋元件的固定位置的光学对准。

公开(公告)号：US09301405B1

公开(公告)日：2016-03-29

申请号：US14604956

申请日：2015-01-26

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yi-Fan Kao ,  Jaen-Don Lan ,  Yu-Te Lu ,  Yung-Lin Chia ,  An-Ping Tseng

IPC: H01L21/4763 ,  H05K3/40 ,  H05K3/06 ,  H05K3/00 ,  H05K3/18 ,  H05K3/02 ,  H05K1/09 ,  H05K1/11 ,  H01L21/48

CPC classification number: H05K3/0035 ,  H01L21/4857 ,  H01L2924/01078 ,  H01L2924/014 ,  H05K1/115 ,  H05K3/007 ,  H05K3/064 ,  H05K3/421 ,  H05K3/429 ,  H05K2201/09536

Abstract: A method for manufacturing microthrough-hole includes electroplating a metal layer on a carrier plate, patterning the metal layer to form a first circuit having copper pads, covering the first circuit with a photoresist layer and not covering the copper window between two of the copper pads, etching the metal layer beneath the copper window and removing the photoresist layer, sequentially forming an insulation layer and a second circuit on the first circuit and the copper window, the second circuit layer having a stop pad corresponding to the copper window, removing the carrier plate, upward drilling through the insulation layer between the stop pad and the copper window to form a microthrough-hole beneath the stop pad, and forming a conductive layer in the microthrough-hole to form the microthrough-hole connecting the first and second circuits. The microthrough-hole and its occupied area is greatly reduced, thereby achieving high circuit density.

Abstract translation: 一种用于制造微通孔的方法包括在载体板上电镀金属层，图案化金属层以形成具有铜焊盘的第一电路，用光致抗蚀剂层覆盖第一电路，并且不覆盖两个铜焊盘之间的铜窗 蚀刻铜窗下方的金属层并除去光致抗蚀剂层，在第一电路和铜窗上依次形成绝缘层和第二电路，第二电路层具有对应于铜窗的停止焊盘，移除载体 通过止动垫和铜窗之间的绝缘层向上钻孔，以在止动垫下方形成微通孔，并在微通孔中形成导电层，形成连接第一和第二电路的微通孔。 微通孔及其占用面积大大降低，从而实现高电路密度。

公开(公告)号：US20160374206A1

公开(公告)日：2016-12-22

申请号：US14742070

申请日：2015-06-17

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Jaen-Don Lan ,  PIN-CHUNG LIN ,  CHEN-RUI TSENG ,  CHENG-EN HO ,  YU-AN CHEN

IPC: H05K3/00 ,  B23K26/402 ,  H05K3/16 ,  B23K26/386

CPC classification number: B23K26/402 ,  B23K26/382 ,  B23K26/389 ,  B23K2101/40 ,  B23K2103/172 ,  B23K2103/30 ,  B23K2103/42 ,  B23K2103/50 ,  H05K3/426 ,  H05K3/4644 ,  H05K2201/0341

Abstract: Disclosed is a method for manufacturing a circuit board, including preparing a substrate having a resin layer and a stop layer, forming at least one conduction hole penetrating the resin layer and stopping at the stop layer, forming a first metal layer through a sputtering process, forming a second metal layer on the first metal layer through a chemical plating process, forming a third metal layer having a circuit pattern, exposing part of the second metal layer and filling up the conduction hole through an electroplating process, and etching the second metal layer and the first metal layer under the second metal layer to expose the resin layer under the first metal layer. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and stable. The etched circuit pattern has a line width/pitch less than 10 μm for fine line width/pitch.

Abstract translation: 公开了一种制造电路板的方法，包括制备具有树脂层和停止层的基板，形成穿过树脂层的至少一个导电孔并在停止层处停止，通过溅射工艺形成第一金属层， 通过化学镀工艺在第一金属层上形成第二金属层，形成具有电路图案的第三金属层，暴露第二金属层的一部分并通过电镀工艺填充导电孔，并蚀刻第二金属层 以及第二金属层下面的第一金属层，以暴露第一金属层下的树脂层。 由于第一金属层提供优异的表面性质，所以第二和第三金属层是良好固定和稳定的。 蚀刻电路图案对于细线宽/间距具有小于10μm的线宽/间距。

公开(公告)号：US20160372409A1

公开(公告)日：2016-12-22

申请号：US14742098

申请日：2015-06-17

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Jaen-Don Lan ,  PIN-CHUNG LIN ,  CHEN-RUI TSENG ,  CHENG-EN HO ,  YU-AN CHEN

IPC: H01L23/498

CPC classification number: H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49866 ,  H01L23/49894

Abstract: Disclosed is a circuit board structure, including the first, second and third metal layers sequentially stacked on the substrate from bottom to top and formed by the sputtering process, the chemical plating process and the electroplating process, respectively. The substrate includes the stop layer and the resin layer stacked on the stop layer. The stop layer includes a pattern having at least one contact region, which is not covered by the resin layer. The first, second and third metal layers have an etched circuit pattern, respectively, and each of the etched circuit patterns is provided out of the corresponding contact region and aligned to each other to expose part of the resin layer. The etched circuit pattern is used for electrical connection. Since the first metal layer provides excellent surface properties, the second and third metal layers are well fixed and more stable.

Abstract translation: 公开了一种电路板结构，其包括分别从底部到顶部依次层叠在基板上的第一，第二和第三金属层，并通过溅射工艺，化学镀工艺和电镀工艺形成。 基板包括停止层和层叠在停止层上的树脂层。 止挡层包括具有至少一个不被树脂层覆盖的接触区域的图案。 第一，第二和第三金属层分别具有蚀刻电路图案，并且每个蚀刻电路图案被提供在相应的接触区域之外并且彼此对准以暴露部分树脂层。 蚀刻电路图案用于电连接。 由于第一金属层提供优异的表面性质，所以第二和第三金属层是良好固定的并且更稳定。

公开(公告)号：US20160262267A1

公开(公告)日：2016-09-08

申请号：US14641016

申请日：2015-03-06

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yi-Fan Kao ,  Jaen-Don Lan ,  Yung-Lin Chia ,  An-Ping Tseng

IPC: H05K3/06 ,  H05K3/00 ,  H05K1/18

CPC classification number: H05K3/064 ,  H01L23/5389 ,  H05K1/185 ,  H05K1/188 ,  H05K3/0008 ,  H05K3/108 ,  H05K3/305 ,  H05K3/425 ,  H05K2201/09563 ,  H05K2201/10674 ,  H05K2203/166

Abstract: A method for manufacturing a circuit board with a buried element having high density pin count, wherein a micro copper window formed in a first circuit by patterned dry film electroplating is easily controlled less than 50 μm so that the micro conduction holes formed after the laser drilling each has a diameter greatly shrunk less than 50 μm so as to highly increase density of the micro conduction holes, thereby facilitating in burial of the buried element with the high density pin count. Additionally, by disposing the micro conduction holes in the same elevation, optically aligning a fixing position for the buried element can be controlled precisely.

Abstract translation: 一种制造具有高密度引脚数的埋入元件的电路板的方法，其中通过图案化干电镀电镀形成在第一电路中的微铜窗容易控制在小于50μm，从而在激光钻孔之后形成的微导电孔 每个具有大大缩小到小于50μm的直径，从而高度增加微通孔的密度，从而便于以高密度引脚数掩埋埋入元件。 此外，通过将相同高度的微通孔设置在一起，可精确地控制掩埋元件的固定位置的光学对准。