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    Cryocooler with variable compression depending on variations in load
    2.
    发明授权
    Cryocooler with variable compression depending on variations in load 无效
    根据负荷变化，CRYOCOOLER可变压缩

    公开(公告)号：KR101175938B1

    公开(公告)日：2012-08-22

    申请号：KR20120079964

    申请日：2012-07-23

    Applicant: KOREA AEROSPACE RES INST

    Inventor： RHEE JU HUN ,  LEE KYUNG HWAN ,  HYUN BUM SEOK ,  SIM EUN SUP

    IPC: F25B9/00 ,  F25B49/00

    CPC classification number: F25B9/14 ,  F25B2400/073

    Abstract: PURPOSE: A cryogenic cooler with variable compression according to load variation is provided to reduce waste power consumption by variable compression-controlling the cooling performance according to the change of the load of the cryogenic cooler. CONSTITUTION: A cryogenic cooler(100) with variable compression comprises a cylinder(110), a piston(120), a connecting rod(130), a linear motor(140), and a sleeve(150). The cylinder is filled with gas. The piston is reciprocated in the cylinder. The linear motor is installed to face the extension portion of the connecting rod and reciprocates the shaft(141) of a motor in the connecting rod direction. The sleeve is formed in cylindrical shape and comprises opening portions in the both sides.

    Abstract translation: 目的：提供根据负载变化可变压缩的低温冷却器，以通过根据低温冷却器的负载变化可变地压缩控制冷却性能来减少浪费功率消耗。 构成：具有可变压缩的低温冷却器（100）包括圆筒（110），活塞（120），连杆（130），线性马达（140）和套筒（150）。 气瓶充满气体。 活塞在气缸中往复运动。 线性马达安装成与连杆的延伸部分相对，并使马达的轴（141）在连杆方向上往复运动。 套筒形成为圆筒形，并且包括两侧的开口部。

    Board assembly for fpga element test using fmc
    3.
    发明授权
    Board assembly for fpga element test using fmc 无效
    使用FMC的FPGA元件测试板组件

    公开(公告)号：KR101147141B1

    公开(公告)日：2012-05-25

    申请号：KR20100129742

    申请日：2010-12-17

    Applicant: KOREA AEROSPACE RES INST

    Inventor： KO DAI HO ,  SIM EUN SUP

    IPC: G01R31/28

    Abstract: PURPOSE: A board assembly for testing a field programmable gate array device using a field programmable gate array mezzanine card is provided to be utilized regardless of a kind of a field programmable gate array and increase data transmission speed while using a universal control board. CONSTITUTION: A board assembly for testing a field programmable gate array(FPGA) device comprises a test board(110) and a control board(120). The test board includes the FPGA device to be tested on the test board. The control board is connected to the test board in an FPGA mezzanine card mode. The control board controls the test board and receives data from the FPGA device for testing the FPGA device. The test board comprises a substrate(111), an high pin count terminal(113), and a low pin count terminal(114). The FPGA device is mounted on the substrate. The high pin count terminal is installed on the substrate and transmits data generated from the calculation of the FPGA device to the control board. The low pin count terminal transmits data generated from the calculation of the FPGA device and files which comprise the FPGA device to the control board.

    Abstract translation: 目的：提供使用现场可编程门阵列夹层卡测试现场可编程门阵列器件的电路板组件，无论现场可编程门阵列如何，并在使用通用控制板时提高数据传输速度。 构成：用于测试现场可编程门阵列（FPGA）装置的电路板组件包括测试板（110）和控制板（120）。 测试板包括要在测试板上测试的FPGA器件。 控制板以FPGA夹层卡模式连接到测试板。 控制板控制测试板，并从FPGA设备接收数据以测试FPGA器件。 测试板包括衬底（111），高引脚数端子（113）和低引脚数端子（114）。 FPGA器件安装在基板上。 高引脚数端子安装在基板上，并将从FPGA器件计算产生的数据传输到控制板。 低引脚数端子将从FPGA器件的计算产生的数据和构成FPGA器件的文件发送到控制板。

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