1.
    发明专利
    失效

    公开(公告)号:JPH05342871A

    公开(公告)日:1993-12-24

    申请号:JP34420092

    申请日:1992-12-24

    Abstract: PURPOSE: To reduce the delay time of a sensing operation by switch transistor for permitting assigning a load transistor pair of a sense amplifier group to each sense amplifier and providing a switch transistor which separates the output node of the amplifier and a main amplifier. CONSTITUTION: The output signal waveform of a column decoder 120 is delayed for a time required for permitting a signals of the output node pair 111 and 112 in a sense back-up circuit 100 to reach a prescribed reference level by a delay element 17 which is connected between an output node pairs 113 and 114 being different from plural sense amplifiers so as to be added to the gates of transistors Tr 15 and 16. Thus, Trs 15 and 16 are made to be in a conductive state, metallic line parasite capacitances 10 and 20 are connected to the nodes 111 and 112, the voltage of the node 111 is rapidly lowered and the voltage of the node 112 is lowered relatively gradually. Then, the main amplifier 30 is operated when control signals CNTL1 and CNTL2 are inputted and the voltages of the nodes 113 and 114 are instantaneously separated.

    CAPACITOR TYPE VOLTAGE DISTRIBUTION CIRCUIT

    公开(公告)号:JPH07202705A

    公开(公告)日:1995-08-04

    申请号:JP29988094

    申请日:1994-12-02

    Abstract: PURPOSE: To provide an accurate capacitor type voltage divider circuit having reduced power consumption by utilizing capacitor system instead of an existing resistor system. CONSTITUTION: Plural switching sections 311 to 313 are driver in accordance with predetermined 1st and 2nd clock signals 301, 305 and provide three reference voltage levels VR, VM, VSS to respective voltage divider capacitors 323, 324. A voltage divider section divides the reference voltage levels VR, VM, VSS to required values. In this case, output voltage (Vri) is expressed by Vri=(VR×Ci2+VSS×Ci1)/(Ci1+Ci2), where Ci1, Ci2 are voltage dividing capacitance values.

    COMPARATOR CIRCUIT OF LOW ELECTRIC WASTE TYPE

    公开(公告)号:JPH07202651A

    公开(公告)日:1995-08-04

    申请号:JP29977094

    申请日:1994-12-02

    Abstract: PURPOSE: To suppress the consumption of currents by instantaneously changing the signal levels of two output terminals for outputting current signals when the logical level of a latch signal is changed, and in steady operation, outputting no current signal. CONSTITUTION: At the time of latch operation holding a latch signal LB at a high logical level, current signals I51, I52 converted by a signal conversion part 50 are supplied to transistors(TRs) Q81, Q82 in an amplification/ determination part 80 through TRs Q64, Q62 in a switching part 60. When the signal LB is at a low logical level and there is no latch operation, the voltage levels of output terminals OUT1, OUT2 are held at a high logical level by a high level holding part 70 to set up an output holding state. Only during a steady operation, a circuit current is turned to '0' by the output signal feedback of an output feedback part 90. Consequently only when the logical level of the signal LB is changed, the signal levels of the terminals OUT1, OUT2, are instantaneously changed and allowed to flow out from the comparator. Since there is no current outflow during stready operation, current consumption can be suppressed.

Patent Agency Ranking