公开(公告)号：JPH0669219A

公开(公告)日：1994-03-11

申请号：JP13751493

申请日：1993-06-08

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIN KITOU ,  GU YOUSHIYO ,  KAN TAIGEN ,  GU CHINKON

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/732

Abstract: PURPOSE: To improve the integration of a logic circuit by constituting a bipolar device as an upward-structure type, including an isolation oxide film, filled in a trench formed in a semiconductor substrate. CONSTITUTION: An n -embedded layer 2 is formed on a silicon substrate 1, on which layer an emitter is formed. A silicon layer 3 is formed on the n - embedded layer 2 which a low-temperature growing method, on which layer a substantial base is formed. After completion of the formation of a field oxide film 9, there are formed on the semiconductor substrate 1 the sequence, an N -polycrystalline silicon 10, a silicide 11, a low-temperature deposited oxide film 12, and a polycrystalline silicon layer 13. In succession, after an N - polycrystalline silicon electrode and a collector region are defined with a fine pattern formation method the layers 10 to 13 are selectively removed with a dry etching method. Operating voltage and a switching speed of an IIL circuit are improved by making equal the upward operating characteristic and downward operating characteristic of the bipolar device. Hereby, in the case of an ECL circuit, integration is enhanced sharply while keeping speed performance.

公开(公告)号：JPH10190002A

公开(公告)日：1998-07-21

申请号：JP33266997

申请日：1997-12-03

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KYO CHINEI ,  GU CHINKON ,  KAKU MEISHIN

IPC: H01L29/78 ,  H01L21/336 ,  H01L27/085 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a structure capable of preventing current leakage in an field effect high voltage device of not less than 100V class whose source-drift region-drain using an SOI(silicon on insulator) structure is disposed horizontally. SOLUTION: Included are a vertical isolation trench 101 defining an active region on a substrate 301 having an SOI structure, a vertical isolation trench oxide film 48 formed inside the vertical isolation trench 101, a source 41 and a drift region 43 and a drain 52 formed horizontally in the active region, and a horizontal gate 44 formed on the upper side of the boundary part between the source 41 and the drift region 43. A plurality of vertical trench gate 45 are provided so that they are separated and formed to have a predetermined spacing, they are insulated from the substrate by an oxide film 46, and they are formed to have a predetermined area.

公开(公告)号：JPH10190000A

公开(公告)日：1998-07-21

申请号：JP24041597

申请日：1997-08-21

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KYO CHINEI ,  GU CHINKON ,  KAKU MEISHIN

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To minimize a junction leakage current by electrically isolating a channel region and a stray region using an insulator wall and to enhance the reliability of an element by suppressing the generation of an abnormal current due to impact ionization. SOLUTION: A wall of silicon dioxide electric insulator 44 is formed between a channel region 41 and a stray region 42. Since a part 41a for forming a p-n junction is not present on surfaces other than the surface of the channel region 41 and the stray region 42, leakage current is minimized and ionization through initial collision is prevented. Furthermore, a passage of current flowing into a source 47 is blocked by the insulator 44, and generation of ions due to secondary collisions in the stray region 42 and increase of abnormal current can be suppressed. According to the structure, operational reliability of an element can be enhanced.

公开(公告)号：JPH08236520A

公开(公告)日：1996-09-13

申请号：JP28700995

申请日：1995-11-06

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： BOKU SATOSHI ,  GU CHINKON

IPC: H01L21/768 ,  H01L21/265 ,  H01L21/31 ,  H01L21/316

Abstract: PROBLEM TO BE SOLVED: To harden an SOG film so that any residual substance can not be generated by forming a second insulating film by SOG on a first insulating film on a substrate, operating a low temperature processing and a plasma processing for hardening the second insulating film, and forming a third insulating film. SOLUTION: A first insulating film 5 is formed by forming an oxide film by a PECVD method. The spin coating of SOG substances is operated for flattening the surface so that a second insulating film 7 can be formed. A low temperature thermal processing is executed several times while a temperature is successively increased, and solvent components, volatile organic components, and moisture excluding organic substances used as coupling agent included in the second insulating film 7 are removed. A plasma processing is executed to the second insulating film 7, and residual substances such as Si-OH, H2 O, solvent, and volatile organic substances are removed so that a membranous quality with high elasticity can be formed. A third insulating film 9 is formed so that an insulating layer 11 can be completed. Thus, it is possible to prevent the current/voltage characteristics of the SOG film from being deteriorated.

公开(公告)号：JPH06310496A

公开(公告)日：1994-11-04

申请号：JP7595694

申请日：1994-04-14

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： BOKU SATOSHI ,  GU CHINKON

IPC: H01L21/31 ,  B05C11/08 ,  H01L21/027 ,  H01L21/28 ,  H01L21/316

Abstract: PURPOSE: To uniformly coat a planarizing material on the entire surface of a wafer being rotated. CONSTITUTION: During rotating of a fixing plate by the rotating force of a motor, an SOG material is coated on a wafer with feeding a thermal energy on the marginal face of the wafer. The thermal energy reduces the viscosity coefficient of the SOG material during rotating at the edge of the wafer 11 being heated by this energy and hence the surface tension near the edge reduces to thereby coat the SOG material at a uniform thickness.