公开(公告)号：JPH0193159A

公开(公告)日：1989-04-12

申请号：JP17827188

申请日：1988-07-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIN KOUSHIYU ,  SAI SOUKUN ,  GU YOUSHIYO ,  KIN JIYOKAN ,  RI SHINKOU

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

Abstract: PURPOSE: To ensure high speed and high integration characteristics by simultaneously fabricating a high speed bipolar transistor with self alignment of polycrystalline Si and a high integration CMOS device using one wafer. CONSTITUTION: The surface of a P type substrate (Si wafer) 1 is ion implanted with As using a buried layer mask to form N type buried layers 2, 3 and an N type epitaxial layer 4 is grown over the entire surface of the substrate. The layer 4 is ion implanted with B using an oxide film mask to form a P type well 5, and after the oxide film is formed, a Si3 N4 film is deposited. The inside of the layer 4 is ion implanted with B to form a P type junction isolation layer 6, and an oxide film is grown, and further a device isolation region 7 and an insulating layer 8 are formed. B, P are implanted using a mask to form a P type base region 9 and an N type collector region 10, and As is implanted to form an N type polycrystal Si layer 11 on which an oxide film 12 is deposited. Then, gates 13, 14, an emitter 15, and a collector 16 are simultaneously formed. Further, sources/drains 17, 18 and 19, 20 are formed.

公开(公告)号：JPH0669219A

公开(公告)日：1994-03-11

申请号：JP13751493

申请日：1993-06-08

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIN KITOU ,  GU YOUSHIYO ,  KAN TAIGEN ,  GU CHINKON

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/732

Abstract: PURPOSE: To improve the integration of a logic circuit by constituting a bipolar device as an upward-structure type, including an isolation oxide film, filled in a trench formed in a semiconductor substrate. CONSTITUTION: An n -embedded layer 2 is formed on a silicon substrate 1, on which layer an emitter is formed. A silicon layer 3 is formed on the n - embedded layer 2 which a low-temperature growing method, on which layer a substantial base is formed. After completion of the formation of a field oxide film 9, there are formed on the semiconductor substrate 1 the sequence, an N -polycrystalline silicon 10, a silicide 11, a low-temperature deposited oxide film 12, and a polycrystalline silicon layer 13. In succession, after an N - polycrystalline silicon electrode and a collector region are defined with a fine pattern formation method the layers 10 to 13 are selectively removed with a dry etching method. Operating voltage and a switching speed of an IIL circuit are improved by making equal the upward operating characteristic and downward operating characteristic of the bipolar device. Hereby, in the case of an ECL circuit, integration is enhanced sharply while keeping speed performance.

公开(公告)号：JPH05326854A

公开(公告)日：1993-12-10

申请号：JP27369991

申请日：1991-10-22

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： SAI SOUKUN ,  GU YOUSHIYO ,  KIN KOUSHIYU ,  MINAMI MOTOMORI

IPC: H01L21/8249 ,  H01L27/06

Abstract: PURPOSE: To reduce the capacitive components of parts by reducing the inactive base region of a bipolar transistor and source-drain region of a CMOS transistor. CONSTITUTION: This method comprises the steps of depositing a crystal Si film 8, oxide film 9 and nitride film 10 to form emitters and collectors of bipolar elements and gates of CMOS elements, forming an oxide film 11 and second oxide film 12 at both side faces of a polycrystalline Si film 18, etching the exposed surface of an epitaxial layer 3, forming a third nitride film 13 on the side faces of a second nitride film, growing an oxide film 14 on the epitaxial layer 3, removing the nitride films 10, 12, 13 to expose an epitaxial layer 16, implanting impurities in this layer 16 to form p -type regions portions 17 for forming base regions of the bipolar elements and source and drain regions of PMOS elements, and forming n -type regions at portions 18 for forming source and drain regions of NMOS elements.