SUCCESSIVE APPROXIMATION ANALOGUE-DIGITAL CONVERTER AND CONVERSION METHOD

    公开(公告)号:JP2001358589A

    公开(公告)日:2001-12-26

    申请号:JP2001119402

    申请日:2001-04-18

    Abstract: PROBLEM TO BE SOLVED: To provide a successive approximation analog-digital conversion which functions well even when converting such analogue signal as changes slow into a digital signal. SOLUTION: The successive approximation analogue/digital converter which comprises a control logic circuit 1 time-controlled by an external clock signal comprises a digital/analogue converter 2 which converts a second digital D supplied from the control logic circuit into an analogue signal A, and a comparator 3 which compares the analogue signal A with an analogue signal B inputted into the analogue-digital converter. The analogue-digital converter is provided with devices 4 and 20 which increases the analogue signal A, by a preset value Voffs, which is outputted from the digital-analogue converter 2 and inputted in the comparator when the bit of first digital signal D1 that corresponds, by position, to the bit of second digital signal D which is required to be decided during clock cycle is zero.

    3.
    发明专利
    未知

    公开(公告)号:DE60019736D1

    公开(公告)日:2005-06-02

    申请号:DE60019736

    申请日:2000-06-02

    Inventor: BARDELLI ROBERTO

    Abstract: The present invention relates a frequency multiplier circuit and a controlling method thereof, characterised in that it measures a period (Tc) of a waveform by a fixed frequency timing signal (fsys), and that it reproduces said period (Tc) by approaching a number of prefixed length (Tsys) subperiods as equal as possible to each other so to minimise the reproduction error ( epsilon ) thanks to the interpretation of said subperiod number (m) in the following manner m = j * 2 .

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