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    METHOD FOR CONTROLLING VOLTAGE OF HVLDMOS CIRCUIT BOARD
    1.
    发明专利
    METHOD FOR CONTROLLING VOLTAGE OF HVLDMOS CIRCUIT BOARD 失效

    公开(公告)号：JPH1168530A

    公开(公告)日：1999-03-09

    申请号：JP17706298

    申请日：1998-06-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GENOVA ANGELO ,  TARANTOLA MARIO ,  CANTONE GIUSEPPE ,  GARIBOLDI ROBERTO

    IPC: H03K17/06

    Abstract: PROBLEM TO BE SOLVED: To provide a circuit, capable of more efficiently charging a capacitance without increasing the power consumption for a parasitic transistor. SOLUTION: A circuit that charges a capacitance C with an LDMOS-LD integrated transistor is provided with a switching means SWb controlled by a logical signal UVLO. Hereby, the switching means SWb is made into active state, in order to charge a board node with the current whose maximum value is restricted to the pre-established value during a phase, in which a supply voltage Vs of an integrated circuit is lower than the minimum switch-on voltage of the same integrated circuit.

    TURN-OFF CIRCUIT FOR LDMOS WHEN REVERSE CURRENT EXISTS
    2.
    发明专利
    TURN-OFF CIRCUIT FOR LDMOS WHEN REVERSE CURRENT EXISTS 失效

    公开(公告)号：JPH1174769A

    公开(公告)日：1999-03-16

    申请号：JP17734198

    申请日：1998-06-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TARANTOLA MARIO ,  CANTONE GIUSEPPE ,  GENOVA ANGELO ,  GARIBOLDI ROBERTO

    IPC: H03K17/06 ,  H03K17/08

    Abstract: PROBLEM TO BE SOLVED: To automatically switch off an LDMOS transistor by having a zener diode which is biased forward between a supply node and a source node of an LDMOS transistor and providing a 2nd zener diode in place of a charging diode. SOLUTION: A 1st Zener diode Z1 is used in place of a charging diode of a capacity Cp which exists at Vs supply voltage. A 2nd Zener diode Z2 is connected between a source node S of a transistor LD and the supply node Vs. When Zehner voltages VZ1 and VZ2 of the diodes Z1 and Z2 satisfy the condition Vs>VZ1, there holds VTH>VZ1-VZ2, and when Vs Vs+ Vbe-VZ2 holds. VTH is the threshold voltage of the transistor LD, and the difference between the source voltage of the transistor LD and the substrate voltage is equal to VZ2-nVbe.

    SUCCESSIVE APPROXIMATION ANALOGUE-DIGITAL CONVERTER AND CONVERSION METHOD
    3.
    发明专利
    SUCCESSIVE APPROXIMATION ANALOGUE-DIGITAL CONVERTER AND CONVERSION METHOD 失效

    公开(公告)号：JP2001358589A

    公开(公告)日：2001-12-26

    申请号：JP2001119402

    申请日：2001-04-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BARDELLI ROBERTO ,  TARANTOLA MARIO

    IPC: H03M1/38 ,  H03M1/08 ,  H03M1/46

    Abstract: PROBLEM TO BE SOLVED: To provide a successive approximation analog-digital conversion which functions well even when converting such analogue signal as changes slow into a digital signal. SOLUTION: The successive approximation analogue/digital converter which comprises a control logic circuit 1 time-controlled by an external clock signal comprises a digital/analogue converter 2 which converts a second digital D supplied from the control logic circuit into an analogue signal A, and a comparator 3 which compares the analogue signal A with an analogue signal B inputted into the analogue-digital converter. The analogue-digital converter is provided with devices 4 and 20 which increases the analogue signal A, by a preset value Voffs, which is outputted from the digital-analogue converter 2 and inputted in the comparator when the bit of first digital signal D1 that corresponds, by position, to the bit of second digital signal D which is required to be decided during clock cycle is zero.

    PROTECTION CIRCUIT FOR CONTROLLING GATE VOLTAGE OF HVLDMOS TRANSISTOR
    4.
    发明专利
    PROTECTION CIRCUIT FOR CONTROLLING GATE VOLTAGE OF HVLDMOS TRANSISTOR 失效

    公开(公告)号：JPH1168531A

    公开(公告)日：1999-03-09

    申请号：JP17718598

    申请日：1998-06-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TARANTOLA MARIO ,  CANTONE GIUSEPPE ,  GENOVA ANGELO ,  GARIBOLDI ROBERTO

    IPC: H03K17/06 ,  H03K17/0812 ,  H03K17/16

    Abstract: PROBLEM TO BE SOLVED: To surely control a gate voltage so that an LDMOS transistor can not be switched on undesiredly by providing a 2nd inverter provided with an input end, to which a 2nd logical signal is inputted and an output end which is connected to a gate node of the LDMOS transistor. SOLUTION: In a pMOS transistor M1, its source is connected to the cathode of a diode D1 and to a charging terminal of a bootstrap capacitor Cp, also its drain is connected to the drain of an nMOS transistor M2 and to the gate of an LDMOS integrated transistor LD. The source of the transistor M2 is connected to an output node A of a control inverter 101 and to the other terminal of the condenser Cp. Then gates of the transistors M1 and M2 are controlled by a logical signal UVLOb and prevent the transistor LD from being turned on accidentally.

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