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7 records (took 0.021 seconds)

    1.
    发明专利
    未知

    公开(公告)号：DE60329899D1

    公开(公告)日：2009-12-17

    申请号：DE60329899

    申请日：2003-04-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VIMERCATI DANIELE ,  SCHIPPERS STEFAN ,  MIRICHIGNI GRAZIANO ,  VILLA CORRADO

    IPC: G11C16/08 ,  G11C8/08

    Abstract: A circuit (300) is proposed for driving a memory line (110) controlling at least one memory cell (105) of a non-volatile memory device (100), the circuit being responsive to a first and a second selection signals, each one suitable to assume a first logic value or a second logic value, wherein the circuit includes a first level shifter (120s) for converting the first selection signal into a first operative signal and a second level shifter (120g) for converting the second selection signal into a second operative signal, each level shifter including first shifting means (210s, 210g) for shifting one of the logic values of the corresponding selection signal to a first bias voltage, and a selector (140) for applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; in the circuit of the invention each level shifter further includes second shifting means (305s, 305g) for shifting another of the logic values of the corresponding selection signal to the second bias voltage.

    2.
    发明专利
    未知

    公开(公告)号：DE602004009078T2

    公开(公告)日：2008-06-19

    申请号：DE602004009078

    申请日：2004-10-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MIRICHIGNI GRAZIANO ,  MARTINELLI ANDREA

    IPC: G11C16/24

    Abstract: A semiconductor memory device (100) is disclosed. The semiconductor memory device includes a plurality of memory cells (110), arranged according to a plurality of rows and a plurality of column. The memory devices further includes a plurality of bit lines (BL1), each bit line being associated with a respective column of said plurality, and a selecting structure (130b) of the bit lines, to select at least one among said bit lines, keeping the remaining bit lines unselected. The memory device further includes a voltage clamping circuit (210, CL1, CL0, C 1 , C 2 ), adapted to causing the clamping at a prescribed voltage of the unselected bit lines adjacent to a selected bit line during an access operation to the memory.

    5.
    发明专利
    未知

    公开(公告)号：DE602004009078D1

    公开(公告)日：2007-10-31

    申请号：DE602004009078

    申请日：2004-10-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MIRICHIGNI GRAZIANO ,  MARTINELLI ANDREA

    IPC: G11C16/24

    Abstract: A semiconductor memory device (100) is disclosed. The semiconductor memory device includes a plurality of memory cells (110), arranged according to a plurality of rows and a plurality of column. The memory devices further includes a plurality of bit lines (BL1), each bit line being associated with a respective column of said plurality, and a selecting structure (130b) of the bit lines, to select at least one among said bit lines, keeping the remaining bit lines unselected. The memory device further includes a voltage clamping circuit (210, CL1, CL0, C 1 , C 2 ), adapted to causing the clamping at a prescribed voltage of the unselected bit lines adjacent to a selected bit line during an access operation to the memory.

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