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    5.
    发明专利
    未知

    公开(公告)号：DE602006013935D1

    公开(公告)日：2010-06-10

    申请号：DE602006013935

    申请日：2006-03-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MARTINELLI ANDREA ,  SCHIPPERS STEFAN ,  ONORATO MARCO

    IPC: G11C11/56

    Abstract: Method for programming a memory device (30) of the type comprising a matrix of memory cells (35) divided in buffers of cells (35) capacitively uncoupled from each other, the method comprising the steps of: - first programming of said cells (35) belonging to a buffer (B); - second programming of said cells (35) belonging to said buffer (B); said step of first programming occurs with a ramp gate voltage having first pitch (p1) and programs said cells of said buffer (B) with higher threshold distribution and said step of second programming occurs with a ramp gate voltage having pitch (p2) lower than the pitch (p1). The invention also relates to a memory device suitable for implementing the method proposed.

    6.
    发明专利
    未知

    公开(公告)号：DE60307606D1

    公开(公告)日：2006-09-28

    申请号：DE60307606

    申请日：2003-06-04

    Applicant: ST MICROELECTRONICS SRL

    Inventor： SCHIPPERS STEFAN ,  VIMERCATI DANIELE ,  BOLANDRINA EFREM

    IPC: G11C7/14 ,  G11C16/28

    Abstract: A method is described for generating a reference current (Iref) for sense amplifiers (11) connected to cells (12) of a memory matrix (1) comprising the steps of: generating a first reference current analogue signal (REF) through a reference cell (14). Advantageously according to the invention, the method further comprises the steps of: performing an Analog-to-Digital conversion of the first analogue signal (REF) into a reference current digital signal (REF_BITÄ3:0Ü); sending the digital signal (REF_BITÄ3:0Ü) on a connection line (43) to the sense amplifiers (11); and performing a Digital-to-Analog conversion of the digital signal (REF_BITÄ3:0Ü) into a second reference current analogue signal (REF1) to be applied as reference current (Iref) to the sense amplifiers (11). The invention also relates to a reference current generator effective to implement this method.

    8.
    发明专利
    未知

    公开(公告)号：DE60329899D1

    公开(公告)日：2009-12-17

    申请号：DE60329899

    申请日：2003-04-30

    Applicant: ST MICROELECTRONICS SRL

    Inventor： VIMERCATI DANIELE ,  SCHIPPERS STEFAN ,  MIRICHIGNI GRAZIANO ,  VILLA CORRADO

    IPC: G11C16/08 ,  G11C8/08

    Abstract: A circuit (300) is proposed for driving a memory line (110) controlling at least one memory cell (105) of a non-volatile memory device (100), the circuit being responsive to a first and a second selection signals, each one suitable to assume a first logic value or a second logic value, wherein the circuit includes a first level shifter (120s) for converting the first selection signal into a first operative signal and a second level shifter (120g) for converting the second selection signal into a second operative signal, each level shifter including first shifting means (210s, 210g) for shifting one of the logic values of the corresponding selection signal to a first bias voltage, and a selector (140) for applying the first operative signal or a second bias voltage to the memory line according to the second operative signal; in the circuit of the invention each level shifter further includes second shifting means (305s, 305g) for shifting another of the logic values of the corresponding selection signal to the second bias voltage.

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