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    NON-VOLATILE MEMORY HAVING BURST MODE READING FUNCTION AND PAGE MODE READING FUNCTION DURING INTERRUPTION PERIOD OF ELECTRIC CHANGE OPERATION
    2.
    发明专利
    NON-VOLATILE MEMORY HAVING BURST MODE READING FUNCTION AND PAGE MODE READING FUNCTION DURING INTERRUPTION PERIOD OF ELECTRIC CHANGE OPERATION 失效

    公开(公告)号：JP2001057087A

    公开(公告)日：2001-02-27

    申请号：JP2000227222

    申请日：2000-07-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BARTOLI SIMONE ,  BEDARIDA LORENZO ,  SALI MAURO ,  RUSSO ANTONIO

    IPC: G11C16/02

    Abstract: PROBLEM TO BE SOLVED: To obtain a memory having a burst mode reading function and a page mode reading function while erasing or programming one sector in a semiconductor memory having two or more memory sectors S1-S9. SOLUTION: This semiconductor memory is provided with first control circuit means 4, 6 for controlling the electrical change operation of contents of a memory. The first control circuit means 4 (6) can execute selectively the operation for changing electrically one content of a memory sector and can interrupt the execution so as to be possible to reading-access the other memory sectors. The memory is characterized by providing second control circuit means 8, 6 which can permit burst mode reading or page mode reading operation for reading contents of the other memory sectors.

    4.
    发明专利
    未知

    公开(公告)号：DE69633000D1

    公开(公告)日：2004-09-02

    申请号：DE69633000

    申请日：1996-03-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TASSAN CASER FABIO ,  SALI MAURO ,  CANE MARCELLO

    IPC: G11C8/10 ,  G11C16/08 ,  G11C11/00 ,  G11C16/06 ,  G11C8/00

    Abstract: The invention relates to a row decoding circuit (1) for an electrically programmable and erasable semiconductor non-volatile storage device of the type which comprises a matrix (2) of memory cells laid out as cell rows (WL) and columns and is divided into sectors, said circuit being input row decode signals (p,ly,lx,ls) and supply voltages (Vpcxs, pgate) in order to drive an output stage (8) incorporating a complementary pair of high-voltage MOS transistors (M15,M13) of the pull-up and pull-down type, respectively, which are connected to form an output terminal (U) connected to the rows (WL) of one sector of the matrix (2), characterized in that a MOS transistor (M9) of the P-channel depletion type with enhanced gate oxide is provided between the output terminal (U) and the pull-down transistor (M13). The control terminal of the depletion transistor (M9) forms a further input (H) of the circuit (1).

    7.
    发明专利
    未知

    公开(公告)号：DE69940369D1

    公开(公告)日：2009-03-19

    申请号：DE69940369

    申请日：1999-11-25

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BARTOLI SIMONE ,  GERACI ANTONINO ,  SALI MAURO ,  BEDARIDA LORENZO

    IPC: G11C7/00 ,  G11C7/10

    Abstract: The invention relates to a read control circuit portion (1) and an attendant reading method for an electronic memory device (2) integrated in a semiconductor and including a non-volatile memory matrix (4) with associated row and column decoders (5,6) connected to respective outputs of an address counter (7), an ATD circuit (12) for detecting an input transaction as the memory device is being accessed, and read amplifiers (8) and attendant registers (10) for transferring the data read from the memory (2) to the output. The control circuit portion (1) comprises a detection circuit block (15) which is input a clock signal (CK) and a logic signal (BAN) to enable reading in the burst mode, and a burst read mode control logic (3) connected downstream of the circuit block (15). The method of this invention comprises accessing the memory matrix in a random read mode; detecting a request for access in the burst read mode; and executing the parallel reading of a plurality of memory words during a single period of time clocked by a clock signal (CK).

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