公开(公告)号：EP1814121A1

公开(公告)日：2007-08-01

申请号：EP06425047.5

申请日：2006-01-31

Applicant: STMicroelectronics S.r.l.

Inventor： Conte, Antonino ,  Annunziata, Roberto ,  Zuliani, Paola

IPC: G11C16/04 ,  G11C16/08

CPC classification number: G11C16/0433

Abstract: A memory architecture (10) is described of the type comprising at least one matrix (2) of memory cells of the EEPROM type (3) organised in rows or word lines (WL) and columns or bit lines (BL), each memory cell (3) comprising a floating gate cell transistor (MC) and a selection transistor (TS) and being connected to a source line (SL) shared by the matrix (2). The memory cells (3) are organised in words (6), all the memory cells (3) belonging to a same word (6) being driven by a byte switch (5), in turn connected to at least one control gate line (CGT).
Advantageously according to the invention, the memory cells (3) have accessible substrate terminals connected to a first additional line (EEW).
Also a biasing method of a memory architecture is described.

Abstract translation: 描述了包括以行或字线（WL）和列或位线（BL）组织的EEPROM类型（3）的存储器单元的至少一个矩阵（2）的类型的存储器架构（10），每个存储器单元 （3），包括浮置栅极单元晶体管（MC）和选择晶体管（TS），并连接到由矩阵（2）共享的源极线（SL）。 存储单元（3）以单词（6）组织，属于由字节开关（5）驱动的相同单词（6）的所有存储单元（3）依次连接到至少一个控制栅极线 CGT）。 有利地，根据本发明，存储器单元（3）具有连接到第一附加线（EEW）的可访问衬底端子。 还描述了存储器架构的偏置方法。

公开(公告)号：EP0932202B1

公开(公告)日：2006-09-20

申请号：EP97830741.1

申请日：1997-12-31

Applicant: STMicroelectronics S.r.l.

Inventor： Colombo, Paolo ,  Mulatti, Jacopo ,  Campardo, Giovanni ,  Maccarrone, Marco ,  Annunziata, Roberto

IPC: H01L27/00 ,  H01L27/02

CPC classification number: H01L27/0259 ,  H01L27/0251

公开(公告)号：EP0932202A1

公开(公告)日：1999-07-28

申请号：EP97830741.1

申请日：1997-12-31

Applicant: STMicroelectronics S.r.l.

Inventor： Colombo, Paolo ,  Mulatti, Jacopo ,  Campardo, Giovanni ,  Maccarrone, Marco ,  Annunziata, Roberto

IPC: H01L27/00 ,  H01L27/02

CPC classification number: H01L27/0259 ,  H01L27/0251

Abstract: The invention relates to an ESD protection network for a CMOS circuit structure integrated in a semiconductor substrate (2) and comprising discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one primary voltage supply (Vcc) having a respective primary ground (GND), and from at least one secondary voltage supply (Vcc_IO) having a respective secondary ground (GND_IO). This network comprises essentially:

a first ESD protection element (15) for an input stage of the circuit structure;
a second ESD protection element (5) for an output stage of the circuit structure, the first (15) and second (5) protection elements having an input/output terminal (20) of the integrated circuit structure in common;
at least one ESD protection element (B0) between the primary supply (Vcc) and the primary ground (GND);
at least one ESD protection element (B) between the secondary supply (Vcc_IO) and the secondary ground (GND_IO).

Abstract translation: 本发明涉及一种用于集成在半导体衬底（2）中的CMOS电路结构的ESD保护网络，其包括形成在彼此电绝缘的各个衬底部分中的独立电路块，并且由至少一个初级电压源（Vcc ）具有相应的初级接地（GND），以及具有相应次级接地（GND_IO）的至少一个次级电压源（Vcc_IO）。 该网络基本上包括：用于电路结构的输入级的第一ESD保护元件（15） 用于所述电路结构的输出级的第二ESD保护元件（5），所述第一保护元件（15）和第二保护元件（5）具有所述集成电路结构的输入/输出端子（20）; 主电源（Vcc）和主接地（GND）之间的至少一个ESD保护元件（B0）; 在次级电源（Vcc_IO）和次级接地（GND_IO）之间的至少一个ESD保护元件（B）。

公开(公告)号：EP1403927A1

公开(公告)日：2004-03-31

申请号：EP02425592.9

申请日：2002-09-30

Applicant: STMicroelectronics S.r.l.

Inventor： Zuliani, Paola ,  Giarda, Katia ,  Annunziata, Roberto

IPC: H01L27/105 ,  H01L21/8247

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11534 ,  H01L29/66575

Abstract: A process for fabricating high-voltage drain-extension transistors, whereby the transistors are integrated in a semiconductor substrate (10) along with non-volatile memory cells comprising floating gate transistors, the process comprising at least the following steps:

defining respective active areas (1,2) for HV transistors and floating gate transistors in a common semiconductor substrate (10), with the active areas being separated from each other by insulating regions (3);
depositing a layer (4) of gate oxide onto the active areas;
depositing a layer (5) of polysilicon onto the gate oxide layer (4);
first masking and then etching through the polysilicon layer (5) to form gate regions (7) of the HV transistors;
performing a first dopant implantation to form first portions (9) of the high-voltage transistor junctions;
conformably depositing a dielectric layer (11) onto the whole substrate (10) to provide an interpoly layer of the floating gate transistor;
making openings (12) at the locations of the first portions (9) of the high-voltage transistor junctions;
performing, through the openings (12), a second dopant implantation to form second portions ( 13) of the high-voltage transistor junctions, with the perimetral areas of the gate regions and the active area of the floating gate transistor being screened off by the dielectric layer (11).

Abstract translation: 制造高压漏极延伸晶体管：（a）通过在高压晶体管结的第一部分的位置处形成开口; 和（b）通过开口进行第二掺杂剂注入，以形成高电压晶体管结的第二部分，栅极区域的周边区域和由电介质层屏蔽的浮动栅晶体管的有源区。 与包括浮栅晶体管的非易失性单元一起集成在半导体（10）衬底中的高电压漏极延伸晶体管的制造包括：（a）在公共半导体衬底中定义用于高电压晶体管和浮置栅极晶体管的各自的有效面积 其中所述有源区域通过绝缘区域（3）彼此分离; （b）在有源区上沉积栅极氧化物层（4）; （c）在栅极氧化物层上沉积多晶硅层; （d）通过多晶硅层进行膜掩蔽和蚀刻以形成晶体管的栅极区域（7）; （e）执行第一掺杂剂注入以形成晶体管结的第一部分（9）; （f）顺应地沉积介电层（11）以提供所述浮栅晶体管的多晶硅层; 和（g）通过开口（12）进行第二掺杂剂注入，以形成高电压晶体管结的第二部分（13），栅极区域的周边区域和浮置栅极晶体管的有源区域被电介质层屏蔽 。 在高压晶体管结的第一部分的位置处形成开口。