公开(公告)号：EP0932203B1

公开(公告)日：2009-02-18

申请号：EP97830742.9

申请日：1997-12-31

Applicant: STMicroelectronics S.r.l.

Inventor： Colombo, Paolo ,  Camerlenghi, Emilio

IPC: H01L27/02 ,  H01L29/735

CPC classification number: H01L29/735 ,  H01L27/0259

公开(公告)号：EP1073119B1

公开(公告)日：2004-05-26

申请号：EP99830491.9

申请日：1999-07-30

Applicant: STMicroelectronics S.r.l.

Inventor： Colombo, Paolo

IPC: H01L27/00 ,  H01L27/02

CPC classification number: H01L27/0259

公开(公告)号：EP1011137A1

公开(公告)日：2000-06-21

申请号：EP98830757.5

申请日：1998-12-16

Applicant: STMicroelectronics S.r.l.

Inventor： Colombo, Paolo ,  Maurelli, Alfonso

IPC: H01L21/8239 ,  H01L27/02

CPC classification number: H01L27/11521 ,  H01L27/0266 ,  H01L29/66659

Abstract: A method of forming a doped region (8,9) in an integrated circuit which includes a matrix of memory cells and Lightly Doped Drain (LDD) transistors and which is fabricated by means of a process providing for a Self-Aligned Source (SAS) masked etch and implant and for a selective salicidation of some doped regions, the doped region suitable for forming an integrated resistor and/or an abrupt-profile source/drain region of a transistor. The doped region (8,9) is formed by introducing into a semiconductor layer (2) of a first conductivity type a dopant of a second conductivity type, exploiting the SAS masked implant used to form source regions (5) of the matrix of memory cells. At least a portion of a surface of the doped region (8,9) is prevented from being salicidated by using as a protective mask a portion of a dielectric layer (15) from which insulating sidewall spacers (17) for the LDD transistors are formed.

Abstract translation: 在集成电路中形成掺杂区域（8,9）的方法，其包括存储器单元的一个矩阵和轻掺杂漏极（LDD）晶体管，并且借助于该制造提供一自对准源极（SAS）的处理 掩蔽蚀刻和植入物和用于一些掺杂区域的选择性硅化，适于晶体管的集成电阻和/或突然轮廓源极/漏极区域的形成掺杂区域。 该掺杂区域（8,9）被引入到第一导电类型的第二导电类型的掺杂剂的半导体层（2），利用该SAS掩模注入用来形成源极区域（5）形成的存储器矩阵的 细胞。 至少所述掺杂区域（8,9）的表面的一部分从通过使用作为保护掩模从哪个绝缘侧壁间隔物（17），用于在LDD晶体管的电介质层（15）的一部分被salicidated被防止形成 ，

公开(公告)号：EP0932202B1

公开(公告)日：2006-09-20

申请号：EP97830741.1

申请日：1997-12-31

Applicant: STMicroelectronics S.r.l.

Inventor： Colombo, Paolo ,  Mulatti, Jacopo ,  Campardo, Giovanni ,  Maccarrone, Marco ,  Annunziata, Roberto

IPC: H01L27/00 ,  H01L27/02

CPC classification number: H01L27/0259 ,  H01L27/0251

公开(公告)号：EP0932202A1

公开(公告)日：1999-07-28

申请号：EP97830741.1

申请日：1997-12-31

Applicant: STMicroelectronics S.r.l.

Inventor： Colombo, Paolo ,  Mulatti, Jacopo ,  Campardo, Giovanni ,  Maccarrone, Marco ,  Annunziata, Roberto

IPC: H01L27/00 ,  H01L27/02

CPC classification number: H01L27/0259 ,  H01L27/0251

Abstract: The invention relates to an ESD protection network for a CMOS circuit structure integrated in a semiconductor substrate (2) and comprising discrete circuit blocks formed in respective substrate portions which are electrically isolated from one another and independently powered from at least one primary voltage supply (Vcc) having a respective primary ground (GND), and from at least one secondary voltage supply (Vcc_IO) having a respective secondary ground (GND_IO). This network comprises essentially:

a first ESD protection element (15) for an input stage of the circuit structure;
a second ESD protection element (5) for an output stage of the circuit structure, the first (15) and second (5) protection elements having an input/output terminal (20) of the integrated circuit structure in common;
at least one ESD protection element (B0) between the primary supply (Vcc) and the primary ground (GND);
at least one ESD protection element (B) between the secondary supply (Vcc_IO) and the secondary ground (GND_IO).

Abstract translation: 本发明涉及一种用于集成在半导体衬底（2）中的CMOS电路结构的ESD保护网络，其包括形成在彼此电绝缘的各个衬底部分中的独立电路块，并且由至少一个初级电压源（Vcc ）具有相应的初级接地（GND），以及具有相应次级接地（GND_IO）的至少一个次级电压源（Vcc_IO）。 该网络基本上包括：用于电路结构的输入级的第一ESD保护元件（15） 用于所述电路结构的输出级的第二ESD保护元件（5），所述第一保护元件（15）和第二保护元件（5）具有所述集成电路结构的输入/输出端子（20）; 主电源（Vcc）和主接地（GND）之间的至少一个ESD保护元件（B0）; 在次级电源（Vcc_IO）和次级接地（GND_IO）之间的至少一个ESD保护元件（B）。

公开(公告)号：EP0932203A1

公开(公告)日：1999-07-28

申请号：EP97830742.9

申请日：1997-12-31

Applicant: STMicroelectronics S.r.l.

Inventor： Colombo, Paolo ,  Camerlenghi, Emilio

IPC: H01L27/00 ,  H01L27/02

CPC classification number: H01L29/735 ,  H01L27/0259

Abstract: The invention relates to a method and a related circuit structure for improving the effectiveness of ESD protection in circuit structures realized in a semiconductor substrate (2) overlaid with an epitaxial layer (3) and including at least one ESD protection lateral bipolar transistor (5) realized in the surface of the epitaxial layer (3). The method consists of forming an isolating well (4) from the substrate (2) under the transistor (5).
Advantageously, the bipolar (5) can be fully isolated from the substrate (2) by first (10) and second (11) N wells which extend from the surface of the epitaxial layer (3) down to and in contact with the buried well (4).

Abstract translation: 本发明涉及一种方法和用于提高ESD保护的在半导体衬底覆盖有在外延层（3）（2）来实现的电路结构的效率和包括至少一个ESD保护横向双极性晶体管中的相关的电路结构（5） 实现在外延层（3）的表面上。 形成所述晶体管（5）根据从所述基片（2）分离井（4）的besteht的方法。 有利地，该双极性（5）可以被完全从基板（2）由第一（10）和第二（11）N阱从外延层（3）的表面下降到与接触延伸，以与掩埋阱中分离 （4）。

公开(公告)号：EP1073119A1

公开(公告)日：2001-01-31

申请号：EP99830491.9

申请日：1999-07-30

Applicant: STMicroelectronics S.r.l.

Inventor： Colombo, Paolo

IPC: H01L27/00 ,  H01L27/02

CPC classification number: H01L27/0259

Abstract: The invention relates to an ESD protection device (1) for circuit structures integrated in a semiconductor substrate (2) and having at least one supply terminal (4) arranged to receive a positive or negative voltage potential, the device (1) comprising an ESD protection transistor (T1) formed in the surface of the substrate, inside an isolated region (7) from the substrate (2). This protection device further comprises a second ESD protection transistor (T2) connected in series with the first transistor (T1) and formed in the substrate outside said isolated region (7).

Abstract translation: 本发明涉及一种集成在半导体衬底（2）中的电路结构的ESD保护器件（1），并且具有至少一个用于接收正或负电压电位的电源端子（4），该器件（1）包括ESD 保护晶体管（T1），形成在衬底（2）的隔离区域（7）内的衬底表面。 该保护装置还包括与第一晶体管（T1）串联连接的第二ESD保护晶体管（T2），并形成在所述隔离区域（7）外部的衬底中。