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    Address counter for nonvolatile memory device
    1.
    发明公开
    Address counter for nonvolatile memory device 审中-公开
    AdresszählerfürnichtflüchtigeSpeichervorrichtung

    公开(公告)号：EP1884955A1

    公开(公告)日：2008-02-06

    申请号：EP06425535.9

    申请日：2006-07-28

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Asia Pacific Pte Ltd. ,  Hynix Semiconductor Inc.

    Inventor： Lee, Hyungsang ,  Song, Dae Sik ,  Mulatti, Jacopo

    IPC: G11C8/04

    CPC classification number: G11C8/04 ,  G11C16/08

    Abstract: An address counter for a nonvolatile memory device comprising a memory cell array and a page buffer for storing data read from a selected memory array page and to be read therefrom starting from an addressed memory array location during a read sequence and during data input cycles to the device to be written starting from an addressed memory array location during a program sequence, is composed of a cascade of elementary cells. Each cell includes an address counting flip-flop (F/F2) that is updated to the value of every newly counted address bit (ADD) or latches a column address bit value (ADD) input by an external user of the memory device during ALE cycles for addressing said start memory location on the selected page at the rising edge of a clock signal (CK_ADD) generated by an input logic circuitry managing external user's commands, and a carry signal (CARRY) propagation logic circuit along the cascaded elementary cells.
    Each cell further comprises an additional address loading flip-flop (F/F1) for loading such a column address bit value (LOADADD) input by an external user of the memory device during ALE cycles for addressing a start memory location on a selected page at the rising edge of said clock signal (CK_LOAD) during ALE cycles, and logic circuit means for updating the address counting flip flop (F/F2) at the rising edge of said clock signal (CK_ADD) to said address bit value (LOADADD) when is active an internally generated control signal (ENLOAD) that is raised during a read confirm cycle (30h), in a read sequence, and during a first data input cycle (D0), in a program sequence.
    The new structure prevents glitches and permits to implement multiple internal pipelining buses without employing an adder connected in cascade of the address counter output bus and reducing the possibility of glitches being generated.

    Abstract translation: 一种用于非易失性存储器件的地址计数器，包括存储器单元阵列和页缓冲器，用于存储从所选择的存储器阵列页读取的数据并从读取序列期间从寻址的存储器阵列位置读取数据，并且在数据输入周期期间从其读取 在程序序列期间从寻址的存储器阵列位置开始写入的器件由基本单元级联组成。 每个单元包括地址计数触发器（F / F2），其被更新为每个新计数的地址位（ADD）的值，或锁存由ALE中存储器件的外部用户输入的列地址位值（ADD） 用于在由管理外部用户命令的输入逻辑电路产生的时钟信号（CK_ADD）的上升沿和沿着级联元件单元的进位信号（CARRY）传播逻辑电路中寻址所选择的页面上的所述起始存储器位置的周期。 每个单元还包括用于在ALE周期期间加载由存储器件的外部用户输入的这样的列地址位值（LOADADD）的附加地址加载触发器（F / F1），用于寻址所选页面上的起始存储器位置 在ALE周期期间所述时钟信号（CK_LOAD）的上升沿以及用于在所述时钟信号（CK_ADD）的上升沿将地址计数触发器（F / F2）更新为所述地址位值（LOADADD）的逻辑电路装置， 在读取确认周期（30h），读取序列和第一个数据输入周期（D0）期间在程序序列中激活内部产生的控制信号（ENLOAD）。 新的结构可以防止毛刺和允许实现多个内部流水线总线，而不需要使用连接在地址计数器输出总线级联中的加法器，并减少产生毛刺的可能性。

    Low consumption TTL-CMOS input buffer stage
    2.
    发明公开
    Low consumption TTL-CMOS input buffer stage 失效
    TTL-CMOS Eingangspufferstufe mit geringem Leistungsverbrauch

    公开(公告)号：EP0928068A1

    公开(公告)日：1999-07-07

    申请号：EP97830743.7

    申请日：1997-12-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Mulatti, Jacopo ,  Maccarrone, Marco ,  Martines, Ignazio ,  Micheloni, Rino

    IPC: H03K19/00 ,  H03K19/0185

    CPC classification number: H03K19/0016

    Abstract: The invention relates to a low-consumption TTL-CMOS input buffer stage (10) of the type which comprises a chain of inverters (11,12,13,14) cascade connected between an input (APAD) receiving electric signals at a TTL logic level and an output (ADD) reproducing electric signals at a CMOS logic level, and powered between a first or supply voltage reference (Vcc) and a second or ground reference (GND). Advantageously, the first inverter (11) in the chain includes a means (15,MP2,MN2) of selecting the delivery path to the stage (10) according to an activate signal (LOWPOWER) for a low-consumption operation mode.
    In essence, the first inverter (11) of the buffer (10) has two signal paths, one for normal operation, and the other for low consumption operation.

    Abstract translation: 本发明涉及一种低功耗TTL-CMOS输入缓冲器级（10），其包括串联连接在以TTL逻辑电路接收电信号的输入端（APAD）之间的反相器链（11,12,13,14） 电平和输出（ADD）以CMOS逻辑电平再现电信号，并且在第一或电源电压参考（Vcc）和第二或接地参考（GND）之间供电。 有利地，链中的第一反相器（11）包括根据用于低功耗操作模式的激活信号（LOWPOWER）选择到级（10）的传送路径的装置（15，MP2，MN2）。 实质上，缓冲器（10）的第一反相器（11）具有两个信号路径，一个用于正常操作，另一个用于低功耗操作。

    Improved output circuit for integrated circuits
    5.
    发明公开
    Improved output circuit for integrated circuits 失效
    Verbesserte Ausgangsschaltungfürintegrierte Schaltungen

    公开(公告)号：EP0911974A1

    公开(公告)日：1999-04-28

    申请号：EP97830542.3

    申请日：1997-10-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Mulatti, Jacopo ,  Zanardi, Stefano ,  Golla, Carla Maria ,  Conci, Armando

    IPC: H03K19/003

    CPC classification number: H01L27/0928 ,  H01L27/0251 ,  H03K17/162 ,  H03K19/00361 ,  Y10S257/901

    Abstract: Output circuit for an integrated circuit, comprising first transistor means (P2) and second transistor means (N2) connected in series between a first external voltage (Vcc) and a second external voltage (Gnd) external to the integrated circuit (100), respectively through first (L2) and second electrical connecting means (L4). The first transistor means for carry an output line (5) of the integrated circuit to the first external voltage, while the second transistor means for carry said external line of the integrated circuit to said second external voltage. The second transistor means are formed inside a first well (130) of a first conductivity type contained inside a second well (140) of a second conductivity type formed in a substrate (7) of the first conductivity type. The second well (140) of the second conductivity type is connected to said first external voltage (Vcc) through third electrical connecting means (L21) distinct from said first electrical connecting means (L2).

    Abstract translation: 一种用于集成电路的输出电路，包括分别串联在集成电路（100）外部的第一外部电压（Vcc）和第二外部电压（Gnd）之间的第一晶体管装置（P2）和第二晶体管装置（N2） 通过第一（L2）和第二电连接装置（L4）。 第一晶体管用于将集成电路的输出线（5）传送到第一外部电压，而第二晶体管用于将集成电路的所述外部线路传送到所述第二外部电压。 第二晶体管装置形成在形成在第一导电类型的衬底（7）中的第二导电类型的第二阱（140）内的第一导电类型的第一阱（130）内。 第二导电类型的第二阱（140）通过与所述第一电连接装置（L2）不同的第三电连接装置（L21）连接到所述第一外部电压（Vcc）。

    Power on reset circuit for a digital device including an on-chip voltage down converter
    6.
    发明公开
    Power on reset circuit for a digital device including an on-chip voltage down converter 有权
    包含片上降压转换器的数字设备的上电复位电路

    公开(公告)号：EP1883160A1

    公开(公告)日：2008-01-30

    申请号：EP06425538.3

    申请日：2006-07-28

    Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics Asia Pacific Pte Ltd. ,  Hynix Semiconductor Inc.

    Inventor： Seo, Donghyun ,  Mulatti, Jacopo ,  Kang, Taegyoung

    IPC: H03K17/22 ,  G01F1/24 ,  G01F1/28

    CPC classification number: H03K17/223 ,  G06F1/24 ,  G06F1/28

    Abstract: A power on reset circuit for initializing at power on a digital integrated circuit comprising a first power on reset signal generator (PORE_GEN) supplied by an externally applied power supply voltage (VDDE), generating a first or external power on reset signal (PORE) during external power supply voltage (VDDE) ramp up, a reference voltage generator (REF_GEN) powered by said externally applied power supply voltage (VDDE) when enabled by said first power on reset signal (PORE) for generating a stable compensating reference voltage (VREF_VDC), a voltage down converter circuit (VDC) converting the externally applied power supply voltage (VDDE) to a stable regulated internal supply voltage (VDDI) employing said reference voltage (VREF_VDC) generated by the reference voltage generator, and a second or internal power on reset signal generator circuit (PORI_GEN) supplied at said stable regulated internal supply voltage (VDDI) and generating a second power on reset signal (PORI) conveyed to core parts of the integrated circuit for initializing them at power on, has the second internal power on reset signal generator circuit with enablement means for enabling also the second internal power on reset signal generator circuit with the first power on reset signal (PORE) together with the voltage down converter circuit (VDC).
    Fuse means permit optimization of dynamical responses of the two reset generators for selectably supported external power supply voltages.

    Abstract translation: 一种通电复位电路，用于在数字集成电路上通电时进行初始化，所述数字集成电路包括由外部施加的电源电压（VDDE）提供的第一通电复位信号发生器（PORE_GEN），其在生成期间产生第一或外部通电复位信号（PORE） 当由所述第一通电复位信号（PORE）启用时，外部电源电压（VDDE）斜升，由所述外部施加的电源电压（VDDE）供电的参考电压发生器（REF_GEN），用于产生稳定的补偿参考电压（VREF_VDC） ，使用由参考电压发生器产生的所述参考电压（VREF_VDC）将外部施加的电源电压（VDDE）转换为稳定的经调节的内部电源电压（VDDI）的降压转换器电路（VDC），以及第二或内部电源 在所述稳定的经调节的内部电源电压（VDDI）处提供的复位信号发生器电路（PORI_GEN），并产生传送给cor的第二加电复位信号（PORI） 用于在通电时初始化它们的部分集成电路具有第二内部通电复位信号发生器电路，其具有启用装置，用于启用具有第一通电复位信号（PORE）的第二内部通电复位信号发生器电路以及 降压转换器电路（VDC）。 保险丝意味着可以优化两个复位发生器对于有选择支持的外部电源电压的动态响应。

    Temperature correlated voltage generator circuit and corresponding voltage regulator for a single power memory cell, particularly of the FLASH-type
    10.
    发明公开
    Temperature correlated voltage generator circuit and corresponding voltage regulator for a single power memory cell, particularly of the FLASH-type 失效
    温度相关电压发生器电路和用于提供与单个电源上的存储器单元相关联的电压调节器，特别是闪存类型的

    公开(公告)号：EP0915407A1

    公开(公告)日：1999-05-12

    申请号：EP97830574.6

    申请日：1997-11-05

    Applicant: STMicroelectronics S.r.l.

    Inventor： Mulatti, Jacopo ,  Zammattio, Matteo ,  Ghilardelli, Andrea ,  Carrera, Marcello

    IPC: G05F1/00 ,  G05F3/24

    CPC classification number: G05F3/245 ,  Y10S323/907

    Abstract: The invention relates to a temperature-related voltage generating circuit having an input terminal (15) receiving a control voltage (V BG ) independent of temperature, and an output terminal (16) delivering a temperature-related control voltage (Vout), the input and output terminals (15, 16) being connected together through at least an amplifier stage (19) adapted to set an output reference voltage from a comparison of input voltages, and comprising a generator element (T1) generating a Varying voltage (V BE ) with temperature connected between a ground voltage reference (GND) and a non-inverting input terminal of the amplifier stage (19), which has an output terminal adapted to deliver a multiple of the varying voltage (V BE ) with temperature to an inverting input terminal of a comparator stage (18); the comparator stage (18) has its output connected to the temperature-related voltage generating circuit (14) and a non-inverting input terminal receiving the control voltage (V BG ) independent of temperature to evaluate the difference between the control voltage (V BG ) independent of temperature and said voltage being a multiple of the varying voltage (V BE ) with temperature and to output a temperature-related control voltage (Vout) having at room temperature a mean value which is independent of its thermal differential (δVout/δT) and increases with temperature.
    The invention also relates to a regulator for a drain voltage (Vd) of a single-supply memory cell (M1), comprising a temperature-related voltage generating circuit (14) according to the invention.

    Abstract translation: 本发明涉及具有输入端子（15）的温度相关的电压生成电路接收控制电压（VBG）与温度无关，并提供一个温度相关的控制电压（Vout），所述输入输出端子（16）和 输出端子（15，16）通过连接在一起的至少到放大器级（19）angepasst从输入电压的比较，并包括发电机元件（T1）产生变化的电压（VBE）与温度设定为输出参考电压 连接在地电压基准（GND）和所述放大器级（19），其具有与输出端子angepasst以反转的输入端子提供变化的电压（VBE）随温度的倍数的一个非反相输入端之间 比较器级（18）; 的比较器级（18）具有其输出连接到所述温度有关的电压发生电路（14）和一个非反相输入端接收与温度无关的控制电压（VBG），以评估（VBG）独立于控制电压之间的差 温度和所述电压是所述变化的电压（VBE）的随温度和输出的平均值的所有其是独立于其热差异的（增量比Vout /增量T）在室温下具有的温度相关的控制电压（Vout）的倍数的 随着温度增加而增加。 因此，本发明涉及一种用于一个温度相关的电压发生电路（14）的单电源的存储单元（M1）的漏极电压（Vd）的调节器雅丁于本发明。

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