公开(公告)号：EP1376861B1

公开(公告)日：2009-03-25

申请号：EP03076840.2

申请日：2003-06-13

Applicant: STMicroelectronics S.r.l.

Inventor： Cali', Giovanni ,  Pelleriti, Roberto ,  Torrisi, Felice

IPC: H03F3/45

CPC classification number: H03F3/45085 ,  H03F3/45089 ,  H03F2203/45296 ,  H03F2203/45392 ,  H03F2203/45394 ,  H03F2203/45702

公开(公告)号：EP1643649A1

公开(公告)日：2006-04-05

申请号：EP04425728.5

申请日：2004-09-29

Applicant: STMicroelectronics S.r.l.

Inventor： Bruno, Angela ,  Cali', Giovanni ,  Palleschi, Antonio

IPC: H03L7/197

CPC classification number: H03L7/1978 ,  H03L7/0891

Abstract: The present invention refers to a phase-locked loop comprising an oscillator (10), a phase detector (30) having in input a signal (fr) proportional to the signal in output from the oscillator, a charge pump (50) having in input the signal in output from said phase detector (30), a filter (60) coupled with the charge pump (50), a voltage controlled oscillator (70) and a fractional frequency divider (40). The voltage controlled oscillator (70) is coupled with the filter (60) and sends an output signal (fo) to the fractional frequency divider (40). The fractional frequency divider (40) is adapted to sending an output signal (fv) to the phase detector (30). The phase-locked loop comprises a digital-analogical converter (100) coupled with the charge pump (50) and with the filter (60), an accumulator (80) coupled with the fractional frequency divider (40) and with the digital-analogical converter (100). The fractional frequency divider (40) comprises a prescaler (41) adapted to dividing the signal in input (fo) by a whole number P or by an integer number P+1 and the fractional frequency divider (40) emits a first representative signal (MC) of the division by P or by P+1 of the prescaler (41). The first signal (MC) is in input to the digital-analogical converter (100) so that the signal (Idac) in output from the digital-analogical converter (100) is aligned with the first signal (MC). The phase-locked loop comprises a circuitry (90) coupled to the digital-analogical converter (100) and to the prescaler (41) to synchronize the signal (Idac) in output from the digital-analogical converter (100) with the signal in output (Prout) from the prescaler (41).

Abstract translation: 本发明涉及一种锁相环，包括振荡器（10），相位检测器（30），输入端具有与振荡器的输出信号成比例的信号（fr），具有输入的电荷泵（50） 来自所述相位检测器（30）的输出信号，与所述电荷泵（50）耦合的滤波器（60），压控振荡器（70）和分数分频器（40）。 压控振荡器（70）与滤波器（60）耦合，并将输出信号（fo）发送到分数分频器（40）。 分数分频器（40）适于向相位检测器（30）发送输出信号（fv）。 锁相环包括与电荷泵（50）和滤波器（60）耦合的数模转换器（100），与分数分频器（40）耦合的累加器（80）和数字模拟 转换器（100）。 分数分频器（40）包括预分频器（41），适于将输入（fo）中的信号除以整数P或整数P + 1，分数分频器（40）发射第一代表信号 MC）除以P或P + 1的预分频器（41）。 第一信号（MC）被输入到数模转换器（100），使得从数模转换器（100）输出的信号（Idac）与第一信号（MC）对准。 锁相环包括耦合到数模转换器（100）和预分频器（41）的电路（90），以使来自数模转换器（100）的输出中的信号（Idac）与 输出（Prout）从预分频器（41）。

公开(公告)号：EP1061428B1

公开(公告)日：2005-08-31

申请号：EP99830374.7

申请日：1999-06-16

Applicant: STMicroelectronics S.r.l.

Inventor： Cali', Giovanni ,  Paparo, Mario ,  Pelleriti, Roberto

IPC: G05F1/575

CPC classification number: G05F1/575

公开(公告)号：EP1542111A1

公开(公告)日：2005-06-15

申请号：EP03425791.5

申请日：2003-12-10

Applicant: STMicroelectronics S.r.l.

Inventor： Cali', Giovanni ,  Filoramo, Pietro

IPC: G05F3/26 ,  G05F3/30

CPC classification number: G05F3/30

Abstract: A method of limiting the noise bandwidth of a closed loop bandgap voltage generator generating a stable voltage reference on an output node, comprising a current mirror coupled between the output node and ground, a feedback line including a conducting feedback transistor coupled to an output branch of the current mirror, cooperating with a biasing transistor of the current mirror for keeping constant the collector or drain voltage of the output transistor of the current mirror, and dimensioned such to have the same base-emitter or gate-source voltage of the diode-connected input transistor of the current mirror, a current generator for biasing the feedback transistor by injecting a current into a bias node of the feedback line, and a noise filtering capacitor connected between the bias node and ground, substantially consists in forcing a certain current through the feedback transistor and increasing the resistance of the portion of feedback line in parallel to the capacitor.
This method is implemented in a bandgap voltage generator the feedback line of which comprises circuit means connected between the bias node and the feedback transistor for contributing to force a certain current through the feedback transistor and increasing the resistance of the portion of feedback line in parallel to the capacitor.

Abstract translation: 一种限制闭环带隙电压发生器的噪声带宽的方法，所述闭环带隙电压发生器在输出节点上产生稳定的电压基准，包括耦合在所述输出节点和地之间的电流镜，反馈线包括耦合到输出节点的输出分支的导电反馈晶体管 电流镜，与电流镜的偏置晶体管配合，以保持电流镜的输出晶体管的集电极或漏极电压恒定，并且尺寸使其具有与二极管连接的相同的基极 - 发射极或栅源电压 电流镜的输入晶体管，用于通过将电流注入到反馈线的偏置节点中而偏置反馈晶体管的电流发生器，以及连接在偏置节点和地之间的噪声滤波电容器，其基本上在于迫使一定电流通过 反馈晶体管并且增加反馈线的部分与电容器并联的电阻。 该方法在带隙电压发生器中实现，其反馈线包括连接在偏置节点和反馈晶体管之间的电路装置，用于有助于强制通过反馈晶体管的一定电流并增加反馈部分的电阻 线路与电容器并联。

公开(公告)号：EP1061428A1

公开(公告)日：2000-12-20

申请号：EP99830374.7

申请日：1999-06-16

Applicant: STMicroelectronics S.r.l.

Inventor： Cali', Giovanni ,  Paparo, Mario ,  Pelleriti, Roberto

IPC: G05F1/575

CPC classification number: G05F1/575

Abstract: The invention relates to a low-drop type of voltage regulator (1) formed with BiCMOS/CMOS technology and being of the type which comprises: an input terminal (IN), receiving a stable voltage reference (Vrif) and being connected to one input (-) of an operational amplifier (2) through a switch controlled by a power-on enable signal (CE); a supply voltage reference (Vpos) powering the operational amplifier (2); an output transistor (M1) connected to an output (U) of the amplifier (2) to generate a regulated voltage value (Vreg) to be fed back to the amplifier (2) input; a second transistor (M2) connected in series between the output transistor (M1) and the supply voltage reference (Vpos). The regulator of this invention comprises a control circuit portion (7) connected between the control terminal of the second transistor (M2) and the supply voltage reference (Vpos) to prevent the breakdown of the output transistor (M1) from occurring.

Abstract translation: 本发明涉及一种用BiCMOS / CMOS技术形成的低压型电压调节器（1），其特征在于包括：输入端（IN），接收稳定的电压基准（Vrif）并连接到一个输入端 （ - ）通过由上电使能信号（CE）控制的开关; 为运算放大器（2）供电的电源电压参考（Vpos）; 连接到放大器（2）的输出（U）的输出晶体管（M1），以产生要反馈到放大器（2）输入端的调节电压值（Vreg）; 串联连接在输出晶体管（M1）和电源电压基准（Vpos）之间的第二晶体管（M2）。 本发明的调节器包括连接在第二晶体管（M2）的控制端和电源电压基准（Vpos）之间的控制电路部分（7），以防止输出晶体管（M1）的击穿。

公开(公告)号：EP1643651B1

公开(公告)日：2008-03-05

申请号：EP04425727.7

申请日：2004-09-29

Applicant: STMicroelectronics S.r.l.

Inventor： Bruno, Angela ,  Cali', Giovanni ,  Palleschi, Antonio

IPC: H03M1/74

CPC classification number: H03M1/1061 ,  H03M1/745

公开(公告)号：EP1376861A2

公开(公告)日：2004-01-02

申请号：EP03076840.2

申请日：2003-06-13

Applicant: STMicroelectronics S.r.l.

Inventor： Cali', Giovanni ,  Pelleriti, Roberto ,  Torrisi, Felice

IPC: H03F3/45

CPC classification number: H03F3/45085 ,  H03F3/45089 ,  H03F2203/45296 ,  H03F2203/45392 ,  H03F2203/45394 ,  H03F2203/45702

Abstract: A device for converting a differential signal (Vin1, Vin2) to a single signal (Vout) is described. The device comprises at least one pair of transistors (Q1, Q2) having equal transconductance gain (gm) and which are arranged according a differential stage configuration. The transistors (Q1, Q2) have the differential signal (Vin1, Vin2) in input at the drivable terminals, have first non drivable terminals coupled respectively to first terminals of a first (R1) and a second (Rout) passive elements having second terminals connected with a first supply voltage (VDD), second non drivable terminals coupled to a second supply voltage (VEE) lower than the first supply voltage (VDD). The first terminal of the second passive element (Rout) is the output terminal (OUT) of the device. The last comprises a further transistor (Q3) having a first non drivable terminal connected with the output terminal (OUT) of the device, a second non drivable terminal coupled with said second supply voltage (VEE) and the drivable terminal connected with the first terminal of the first passive element (R1). The further transistor (Q3) has such a transconductance gain (gm3) that the product of said transconductance gain (gm3) by said first passive element (R1) is unitary.

Abstract translation: 描述用于将差分信号（Vin1，Vin2）转换为单个信号（Vout）的装置。 该器件包括具有相等跨导增益（gm）的至少一对晶体管（Q1，Q2），并且根据差分级配置布置。 晶体管（Q1，Q2）在可驱动端子处输入的差分信号（Vin1，Vin2）具有分别耦合到具有第二端子（R1）的第一端（R1）和第二（Rout）无源元件的第一不可驱动端子 与第一电源电压（VDD）连接，第二不可驱动端子耦合到低于第一电源电压（VDD）的第二电源电压（VEE）。 第二无源元件（Rout）的第一个端子是器件的输出端子（OUT）。 最后一个包括具有与该装置的输出端（OUT）连接的第一不可驱动端子的另一个晶体管（Q3），与所述第二电源电压（VEE）耦合的第二不可驱动端子和与第一端子 的第一无源元件（R1）。 另外的晶体管（Q3）具有这样的跨导增益（gm3），所述第一无源元件（R1）的所述跨导增益（gm3）的乘积是一体的。

公开(公告)号：EP0938186A1

公开(公告)日：1999-08-25

申请号：EP98830077.8

申请日：1998-02-19

Applicant: STMicroelectronics S.r.l.

Inventor： Cali', Giovanni ,  Granata, Angelo ,  Palmisano, Giuseppe

IPC: H03F3/00 ,  H03F3/72

CPC classification number: H03F3/72 ,  Y10T307/747 ,  Y10T307/76

Abstract: A circuit for switching a capacitor (C) in an exclusive manner, on the selected one of a plurality of integrated amplifiers (A1, A2, ... AN) comprises a first current generator (IB) connected between a first supply node (VCC) and a first node of the circuit (H), a second current generator (IC) connected between a second supply node (GND) and a second node (L) of the circuit, electrically in parallel to the capacitor (C), an array of switches (S1, S2, ..., SN) of the same number of the integrated amplifiers, exclusively switcheable on, each connecting a directly biased diode (D1, D2, ..., DN) between the first node (H) and the second node (L), each integrated amplifier having a supply node coupled to the connecting node between a respective diode and a respective connecting switch of said array.

Abstract translation: 一种在排他的方式在切换的电容器（C）上的集成放大器（A1，A2，...，AN）的多个所选择的一个电路包括连接在第一电源节点之间的第一电流发生器（IB）（VCC ）和电路（H），连接在第二电源节点（GND）与电路的第二节点（L）之间的第二电流发生器（IC）的第一节点，电并联到电容器（C），以 相同数量的集成放大器的开关（S1，S2，...，SN）的阵列，专可变换上，每个连接的第一节点之间的直接偏置的二极管（D1，D2，...，DN）（H ）和第二节点（L），其具有耦合到二极管和respectivement respectivement连接所述阵列的交换机之间的连接节点供给节点每个集成放大器。

公开(公告)号：EP1542111B1

公开(公告)日：2007-06-27

申请号：EP03425791.5

申请日：2003-12-10

Applicant: STMicroelectronics S.r.l.

Inventor： Cali', Giovanni ,  Filoramo, Pietro

IPC: G05F3/26 ,  G05F3/30

CPC classification number: G05F3/30

公开(公告)号：EP1643651A1

公开(公告)日：2006-04-05

申请号：EP04425727.7

申请日：2004-09-29

Applicant: STMicroelectronics S.r.l.

Inventor： Bruno, Angela ,  Cali', Giovanni ,  Palleschi, Antonio

IPC: H03M1/74

CPC classification number: H03M1/1061 ,  H03M1/745

Abstract: The present invention describes an apparatus for the conversion of a digital input signal (Sx) into a required analogic output signal (Idac). The apparatus comprises first circuit means (1, 5) having said digital input signal (Sx) that is representative of the required output signal (Idac) and suitable for producing a first signal (Imain) on an output line (2) and second circuit means (3, 20) suitable for supplying a second signal (Itrim) on said output line (2) in reply to a further digital signal (Dult). The further digital signal (Dult) is function of external variables (Var) and the union of said first (Imain) and said second (Itrim) signal on said output line (2) forms the required analogic output signal (Idac).

Abstract translation: 本发明描述了一种用于将数字输入信号（Sx）转换成所需的模拟输出信号（Idac）的装置。 该装置包括具有表示所需输出信号（Idac）的所述数字输入信号（Sx）并且适合于在输出线（2）和第二电路（2）上产生第一信号（Imain）的第一电路装置（1,5） 适于在所述输出线（2）上提供第二信号（Itrim）以响应另一数字信号（Dult）的装置（3,20）。 另外的数字信号（Dult）是外部变量（Var）的函数，并且所述输出线（2）上的所述第一（Imain）和所述第二（Itrim）信号的并集形成所需的模拟输出信号（Idac）。