公开(公告)号：EP1408140A1

公开(公告)日：2004-04-14

申请号：EP02425615.8

申请日：2002-10-11

Applicant: STMicroelectronics S.r.l.

Inventor： Carollo, Enzo

IPC: C23C30/00 ,  C23C28/00 ,  C23C14/16

CPC classification number: H01L21/3145 ,  C23C16/345 ,  C23C16/455 ,  C23C16/507 ,  H01L21/3144 ,  H01L21/3185

Abstract: A high-density plasma process (300) is proposed for depositing a layer of Silicon Nitride on a substrate in a plasma reactor. The process includes the steps of: providing (242-255) a gas including precursor components of the Silicon Nitride, generating a plasma applying (220-225) a radio-frequency (RF) power to the gas, and the plasma reacting (260) with the substrate to deposit the layer of Silicon Nitride. In the process of the invention, the total power applied to the gas is in the range from 2.5KW to 4KW, with two different RF power sources (power ratio = 2.1 to 2.5).

Abstract translation: 高密度等离子体工艺包括提供包括氮化硅的前体组分的气体，产生等离子体对气体施加射频功率，以及使等离子体与衬底反应以沉积氮化硅层。 施加到气体的功率为2.5-4 kW。

公开(公告)号：EP2958144A1

公开(公告)日：2015-12-23

申请号：EP15172272.5

申请日：2015-06-16

Applicant: STMicroelectronics S.r.l.

Inventor： Palumbo, Vincenzo ,  Ghidini, Gabriella ,  Carollo, Enzo ,  Toia, Fabrizio Fausto Renzo

IPC: H01L27/08 ,  H01L23/522 ,  H01F17/00 ,  H01F27/28 ,  H01L23/64

CPC classification number: H01F27/32 ,  H01F27/2804 ,  H01F27/323 ,  H01F41/063 ,  H01F2027/2809 ,  H01L23/5227 ,  H01L23/645 ,  H01L27/08 ,  H01L2924/0002 ,  Y10T29/49021 ,  H01L2924/00

Abstract: An integrated transformer (105; 205) integrated transformer comprises a primary winding (135) and a secondary winding (140), of metallic material and having a spiral planar arrangement comprising a corresponding plurality of coils (137; 142). A dielectric portion (145) of dielectric material is arranged between the primary winding and the secondary winding. A field plate winding (150) is electrically coupled with the primary winding. The field plate winding comprises at least one field plate coil (152a) having a lateral extension ( xa ) greater than a lateral extension (xb) of a primary outer coil (137a) of the primary winding with the at least one field plate coil superimposed, in plan view, to the primary outer coil of the primary winding. The field plate winding is configured to mutually separate equipotential surfaces of an operating electric field ( E1; E2 ) at a secondary winding facing edge (139) of the primary outer coil of the primary winding.

Abstract translation: 集成变压器（105; 205）集成变压器包括金属材料的初级绕组（135）和次级绕组（140），并具有包括相应的多个线圈（137,142）的螺旋平面布置。 电介质材料的电介质部分（145）布置在初级绕组和次级绕组之间。 场板绕组（150）与初级绕组电耦合。 场板绕组包括至少一个场板线圈（152a），其具有大于初级绕组的初级外线圈（137a）的横向延伸（xb）的横向延伸（xa），所述初级绕组的主外部线圈（137a）与所述至少一个场板线圈叠加 在平面图中，连接到初级绕组的初级外部线圈。 场板绕组构造成在初级绕组的初级外部线圈的次级绕组面对边缘（139）处相互分离的工作电场（E1; E2）的等电位表面。

公开(公告)号：EP1804293A1

公开(公告)日：2007-07-04

申请号：EP05425942.9

申请日：2005-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Brazzelli, Daniela ,  Servalli, Giorgio ,  Carollo, Enzo

IPC: H01L27/115 ,  H01L21/8247 ,  H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/764 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11534 ,  H01L2924/3011

Abstract: Process for manufacturing a non volatile electronic device integrated on a semiconductor substrate (2) which comprises a plurality of non volatile memory cells (1) being organised in matrix and an associated circuitry, comprising the steps of:
- forming gate electrodes (7) of the memory cells (1) projecting from the semiconductor substrate (2), each of the gate electrodes (7) comprising a first dielectric layer (3), a floating gate electrode (4), a second dielectric layer (5) and a control gate electrode (6) coupled to a respective word line, at least one first portion of the gate electrodes (7) of the memory cells (1) being separated from each other by first openings (15) of a first width (D),
- forming source and drain regions (8) of the memory cells (1) in the semiconductor substrate (2), the source and drain regions (8) of the memory cells (1) being aligned with the gate electrodes (7) of the memory cells (1),
- forming gate electrodes of transistors of the circuitry projecting from the semiconductor substrate (2), each of the gate electrodes of the circuitry comprising a first dielectric layer of the circuitry and a first conductive layer of the circuitry,
- forming source and drain regions of the transistors in the semiconductor substrate (2), the source and drain regions of the transistors being aligned with the gate electrodes (7) of the transistors, the process being characterised in that it comprises the following steps:

- depositing, on the whole device, a third non conform dielectric layer (10) so as to completely fill in the first openings (15) and to form air-gaps (16) between the gate electrodes belonging to the first portion of the gate electrodes (7) of the memory cells (1).

Abstract translation: 一种用于制造集成在半导体衬底（2）上的非易失性电子器件的方法，该半导体衬底包括以矩阵形式组织的多个非易失性存储器单元（1）和相关联的电路，包括以下步骤： - 形成栅电极 从半导体衬底（2）突出的存储单元（1），每个栅电极（7）包括第一介电层（3），浮栅电极（4），第二介电层（5）和控制 栅极电极（6），其耦合到相应的字线，存储单元（1）的栅电极（7）的至少一个第一部分通过第一宽度（D）的第一开口（15）彼此分开， - 在所述半导体衬底（2）中形成所述存储单元（1）的源区和漏区（8），所述存储单元（1）的源区和漏区（8）与所述半导体衬底 存储单元（1）， - 形成所述电路的晶体管的栅电极 在所述半导体衬底（2）中，所述电路的每个栅电极包括所述电路的第一介电层和所述电路的第一导电层， - 形成所述半导体衬底（2）中的所述晶体管的源区和漏区， 晶体管的源极和漏极区域与晶体管的栅电极（7）对准，该工艺的特征在于其包括以下步骤： - 在整个器件上沉积第三非标准电介质层（10） 以便完全填充第一开口（15）并且在属于存储单元（1）的栅电极（7）的第一部分的栅电极之间形成气隙（16）。