公开(公告)号：EP1675180A1

公开(公告)日：2006-06-28

申请号：EP04425936.4

申请日：2004-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Servalli, Giorgio ,  Brazzelli, Daniela

IPC: H01L27/115 ,  H01L21/8247 ,  H01L21/28 ,  H01L29/423

CPC classification number: H01L27/115 ,  H01L21/28273 ,  H01L27/11521

Abstract: A method of making a non-volatile MOS semiconductor memory device includes a formation phase, in a semiconductor material substrate (50), of isolation regions (57) filled by field oxide (65) and of memory cells (500) separated each other by said isolation regions (57). The memory cells (500) include an electrically active region (51) surmounted by a gate electrode (52) electrically isolated from the semiconductor material substrate (50) by a first dielectric layer (53); the gate electrode (52) includes a floating gate (54) defined simultaneously to the active electrically region (51). A formation phase of said floating gate (54) exhibiting a substantially saddle shape including a concavity is proposed.

Abstract translation: 一种制造非易失性MOS半导体存储器件的方法包括：在半导体材料衬底（50）中由场氧化物（65）填充的隔离区（57）和彼此分离的存储单元（500）的形成阶段 所述隔离区（57）。 存储器单元（500）包括由第一介电层（53）与半导体材料衬底（50）电隔离的栅电极（52）覆盖的电有源区（51）; 栅电极（52）包括同时限定到有源电区域（51）的浮栅（54）。 提出了呈现包括凹面的基本鞍形的所述浮动闸门（54）的形成阶段。

公开(公告)号：EP1686620A1

公开(公告)日：2006-08-02

申请号：EP05425034.5

申请日：2005-01-28

Applicant: STMicroelectronics S.r.l.

Inventor： Brazzelli, Daniela ,  Servalli, Giorgio ,  Erbetta, Davide ,  Marangon, Maria Santina

IPC: H01L21/768 ,  H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/115 ,  H01L27/11521

Abstract: In a process for manufacturing a memory (2) having a plurality of memory cells (3) the steps of: forming a well (11), having a first type of conductivity, within a wafer (10) of semiconductor material; defining active regions (12) within the well (11) extending in a first direction (y); forming memory cells (3) within the active regions (12), each memory cell (3) having a source region (15) with a second type of conductivity, opposite to the first type of conductivity; and forming lines of electrical contact (20), which electrically contact source regions (15) aligned in a second direction (x). In the step of forming lines of electrical contact (20), the step of forming an electrical contact between the source regions (15) and portions (37) of the well (11) adjacent thereto in the second direction (x).

Abstract translation: 在用于制造具有存储器单元（3）的步骤的多个A存储器（2）的方法：形成阱（11），具有第一导电类型的半导体材料的晶片（10）内; 在第一方向（Y）延伸的孔（11）内 - 定义的有源区（12）; 有源区域内形成存储单元（3）（12），每个存储单元（3）具有与第二导电类型的，相反于第一导电类型的源极区（15）; 和在第二方向上排列的电接触件（20），该电接触源极区（15）的成型线（X）。 在形成电接触（20），在第二方向（x）的阱（11）与其相邻的源极区（15）和部分（37）之间的电接触形成的步骤的线的步骤。

公开(公告)号：EP1804293A1

公开(公告)日：2007-07-04

申请号：EP05425942.9

申请日：2005-12-30

Applicant: STMicroelectronics S.r.l.

Inventor： Brazzelli, Daniela ,  Servalli, Giorgio ,  Carollo, Enzo

IPC: H01L27/115 ,  H01L21/8247 ,  H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/764 ,  H01L21/76897 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11534 ,  H01L2924/3011

Abstract: Process for manufacturing a non volatile electronic device integrated on a semiconductor substrate (2) which comprises a plurality of non volatile memory cells (1) being organised in matrix and an associated circuitry, comprising the steps of:
- forming gate electrodes (7) of the memory cells (1) projecting from the semiconductor substrate (2), each of the gate electrodes (7) comprising a first dielectric layer (3), a floating gate electrode (4), a second dielectric layer (5) and a control gate electrode (6) coupled to a respective word line, at least one first portion of the gate electrodes (7) of the memory cells (1) being separated from each other by first openings (15) of a first width (D),
- forming source and drain regions (8) of the memory cells (1) in the semiconductor substrate (2), the source and drain regions (8) of the memory cells (1) being aligned with the gate electrodes (7) of the memory cells (1),
- forming gate electrodes of transistors of the circuitry projecting from the semiconductor substrate (2), each of the gate electrodes of the circuitry comprising a first dielectric layer of the circuitry and a first conductive layer of the circuitry,
- forming source and drain regions of the transistors in the semiconductor substrate (2), the source and drain regions of the transistors being aligned with the gate electrodes (7) of the transistors, the process being characterised in that it comprises the following steps:

- depositing, on the whole device, a third non conform dielectric layer (10) so as to completely fill in the first openings (15) and to form air-gaps (16) between the gate electrodes belonging to the first portion of the gate electrodes (7) of the memory cells (1).

Abstract translation: 一种用于制造集成在半导体衬底（2）上的非易失性电子器件的方法，该半导体衬底包括以矩阵形式组织的多个非易失性存储器单元（1）和相关联的电路，包括以下步骤： - 形成栅电极 从半导体衬底（2）突出的存储单元（1），每个栅电极（7）包括第一介电层（3），浮栅电极（4），第二介电层（5）和控制 栅极电极（6），其耦合到相应的字线，存储单元（1）的栅电极（7）的至少一个第一部分通过第一宽度（D）的第一开口（15）彼此分开， - 在所述半导体衬底（2）中形成所述存储单元（1）的源区和漏区（8），所述存储单元（1）的源区和漏区（8）与所述半导体衬底 存储单元（1）， - 形成所述电路的晶体管的栅电极 在所述半导体衬底（2）中，所述电路的每个栅电极包括所述电路的第一介电层和所述电路的第一导电层， - 形成所述半导体衬底（2）中的所述晶体管的源区和漏区， 晶体管的源极和漏极区域与晶体管的栅电极（7）对准，该工艺的特征在于其包括以下步骤： - 在整个器件上沉积第三非标准电介质层（10） 以便完全填充第一开口（15）并且在属于存储单元（1）的栅电极（7）的第一部分的栅电极之间形成气隙（16）。

公开(公告)号：EP1496548B1

公开(公告)日：2008-01-02

申请号：EP03425459.9

申请日：2003-07-11

Applicant: STMicroelectronics S.r.l.

Inventor： Brazzelli, Daniela ,  Baldi, Livio ,  Servalli, Giorgio

IPC: H01L21/762

CPC classification number: H01L21/76229

公开(公告)号：EP1403917A1

公开(公告)日：2004-03-31

申请号：EP02425581.2

申请日：2002-09-26

Applicant: STMicroelectronics S.r.l.

Inventor： Brazzelli, Daniela ,  Clementi, Cesare

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/76235

Abstract: A process for manufacturing semiconductor wafers incorporating differentiated insulating structures envisages the steps of: opening first trenches (8) in a substrate (2) of a semiconductor wafer (1), the trenches delimiting first conductive regions (9) and having a first depth; and opening second trenches (16), delimiting second conductive regions (17) and having a second depth. Furthermore, the step of opening second trenches (16) is preceded by the step of forming first insulating sidewalls (12), which surround the first trenches (8), and is followed by the step of forming second insulating sidewalls (19), which surround the second trenches (16) .

Abstract translation: 该工艺涉及在半导体晶片（1）的衬底（2）中打开沟槽（8），其中沟槽界定导电区域（9）。 绝缘侧壁（12）形成在沟槽（8）周围。 打开另一组沟槽（16）以限定导电区域（17），并且沟槽（16）被绝缘侧壁（19）包围，其中沟槽具有不同的深度。 对于包括绝缘结构的半导体晶片，还包括独立权利要求。

公开(公告)号：EP1675180B1

公开(公告)日：2009-12-09

申请号：EP04425936.4

申请日：2004-12-22

Applicant: STMicroelectronics S.r.l.

Inventor： Servalli, Giorgio ,  Brazzelli, Daniela

IPC: H01L21/8247 ,  H01L21/28

CPC classification number: H01L27/115 ,  H01L21/28273 ,  H01L27/11521

公开(公告)号：EP1496548A1

公开(公告)日：2005-01-12

申请号：EP03425459.9

申请日：2003-07-11

Applicant: STMicroelectronics S.r.l.

Inventor： Brazzelli, Daniela ,  Baldi, Livio ,  Servalli, Giorgio

IPC: H01L21/762

CPC classification number: H01L21/76229

Abstract: This invention relates to a method for manufacturing isolation structures with different depths in a monolithically integrated semiconductor electronic device. The inventive method comprises a first step of defining active areas on a semiconductor material substrate, a second step of forming isolation structures by realising trenches in said substrate and then filling them with field oxide, a third step of defining lithographically at least a first device area, and a fourth step of reducing the vertical height of the substrate and of the field oxide of said first device area.

Abstract translation: 本发明涉及一种用于制造具有不同深度的隔离结构中单片集成半导体电子器件的方法。 本发明方法包括的定义上的半导体材料基板的有源区域的第一步骤中，形成在上述基片由真实伊辛沟槽隔离结构，然后与场氧化物，的限定光刻至少第一器件区域的第三步骤填充它们的第二步骤 ，并减少基板和所述第一器件区的场氧化物的垂直高度的第四步骤。