公开(公告)号：EP1111673A1

公开(公告)日：2001-06-27

申请号：EP01200376.0

申请日：1995-05-10

Applicant: STMicroelectronics S.r.l.

Inventor： Ghidini, Gabriella ,  Clementi, Cesare

IPC: H01L21/8247 ,  H01L21/8239

CPC classification number: H01L27/11526 ,  H01L21/3145 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10844 ,  H01L27/11539

Abstract: The method described provides for the formation of thin thermal oxide on areas of a silicon die intended for memory cells and other components of the peripheral circuits of the memory. To obtain the best dielectrics both for the memory cells and for the components of the peripheral circuits the method comprises a step for high-temperature nitriding of the oxide, a step for removing the nitrided oxide from the areas intended for the components of the peripheral circuits and a step for forming again a nitrided thermal oxide on the exposed areas.

Abstract translation: 所述的方法提供了在用于存储器单元的硅芯片和存储器的外围电路的其它部件的区域上形成薄热氧化物。 为了提高电池氧化物的质量，基本上是由于在存储器的操作期间由于电荷通过它而导致的降解性的降低，该方法提供了氧化物的高温氮化的步骤。 根据一个变型，在用于外围电路的部件的区域上形成的氮化氧化物被除去，然后通过类似的热氧化处理再次形成，然后进行高温氮化。

公开(公告)号：EP2958144A1

公开(公告)日：2015-12-23

申请号：EP15172272.5

申请日：2015-06-16

Applicant: STMicroelectronics S.r.l.

Inventor： Palumbo, Vincenzo ,  Ghidini, Gabriella ,  Carollo, Enzo ,  Toia, Fabrizio Fausto Renzo

IPC: H01L27/08 ,  H01L23/522 ,  H01F17/00 ,  H01F27/28 ,  H01L23/64

CPC classification number: H01F27/32 ,  H01F27/2804 ,  H01F27/323 ,  H01F41/063 ,  H01F2027/2809 ,  H01L23/5227 ,  H01L23/645 ,  H01L27/08 ,  H01L2924/0002 ,  Y10T29/49021 ,  H01L2924/00

Abstract: An integrated transformer (105; 205) integrated transformer comprises a primary winding (135) and a secondary winding (140), of metallic material and having a spiral planar arrangement comprising a corresponding plurality of coils (137; 142). A dielectric portion (145) of dielectric material is arranged between the primary winding and the secondary winding. A field plate winding (150) is electrically coupled with the primary winding. The field plate winding comprises at least one field plate coil (152a) having a lateral extension ( xa ) greater than a lateral extension (xb) of a primary outer coil (137a) of the primary winding with the at least one field plate coil superimposed, in plan view, to the primary outer coil of the primary winding. The field plate winding is configured to mutually separate equipotential surfaces of an operating electric field ( E1; E2 ) at a secondary winding facing edge (139) of the primary outer coil of the primary winding.

Abstract translation: 集成变压器（105; 205）集成变压器包括金属材料的初级绕组（135）和次级绕组（140），并具有包括相应的多个线圈（137,142）的螺旋平面布置。 电介质材料的电介质部分（145）布置在初级绕组和次级绕组之间。 场板绕组（150）与初级绕组电耦合。 场板绕组包括至少一个场板线圈（152a），其具有大于初级绕组的初级外线圈（137a）的横向延伸（xb）的横向延伸（xa），所述初级绕组的主外部线圈（137a）与所述至少一个场板线圈叠加 在平面图中，连接到初级绕组的初级外部线圈。 场板绕组构造成在初级绕组的初级外部线圈的次级绕组面对边缘（139）处相互分离的工作电场（E1; E2）的等电位表面。

公开(公告)号：EP0751560B1

公开(公告)日：2002-11-27

申请号：EP95830282.0

申请日：1995-06-30

Applicant: STMicroelectronics S.r.l.

Inventor： Clementi, Cesare ,  Ghidini, Gabriella ,  Riva, Carlo

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: A process for forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells (1) including an intermediate dielectric multilayer comprising a lower silicon oxide layer (7), an intermediate silicon nitride layer (8) and an upper silicon oxide layer (10) and the simultaneous provision in zones peripheral to the memory cells of at least one first (2) and one second (3) transistor type having gate dielectric of a first and a second thickness respectively. After formation of the floating gate of the cells with a gate oxide layer (5) and a polycrystalline silicon layer (6) and the formation of the lower silicon oxide layer (7) and of the intermediate silicon nitride layer (8), the process in accordance with the present invention includes: removal of said layers from the zones peripheral (R2,R3) to the matrix; formation of a first silicon oxide layer (9) over the substrate in the areas (R2,R3) of both types of transistor (2,3); removal of the preceding layer (9) from areas (R3) assigned only to the transistors (3) of the second type; deposition of said upper silicon oxide layer (10) over the memory cells (1), over the first silicon oxide layer (9) in the areas (R2) of the transistors (2) of the first type and over the substrate (4) in the areas (R3) of the transistors of the second type; and formation of a second silicon oxide layer (11) in the areas (R2,R3) of both types of peripheral transistors (2,3).

公开(公告)号：EP0751559B1

公开(公告)日：2002-11-27

申请号：EP95830281.2

申请日：1995-06-30

Applicant: STMicroelectronics S.r.l.

Inventor： Clementi, Cesare ,  Ghidini, Gabriella ,  Riva, Carlo

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: A process for forming an integrated circuit calls for the provision of at least one matrix of non-volatile memory cells (1) having an intermediate dielectric multilayer including at least a lower dielectric material layer (8) and an upper silicon oxide layer (9) and the simultaneous provision in zones peripheral to the matrix of at least one first transistor type (2) having gate dielectric of a first thickness. After formation of the floating gate with a gate oxide layer (4) and a polycrystalline silicon layer (5) and the formation of the lower dielectric material layer (8), the process in accordance with the present invention calls for: removal of said layers from the peripheral zones (R2) of the matrix; deposition of said upper silicon oxide layer (9) over the memory cells (1),and over the substrate (3) in the areas (R2) of the peripheral transistors (2); and formation of a first silicon oxide layer (10) at least in the areas (R2) of the peripheral transistors (2). To provide additionally a second transistor type having gate dielectric of a second thickness, indicatively thinner than said first thickness, successive steps are added in accordance with the present invention.