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    Method for manufacturing integrated structures including removing a sacrificial region
    2.
    发明公开
    Method for manufacturing integrated structures including removing a sacrificial region 失效
    用于制造包括去除牺牲区域的集成结构的方法

    公开(公告)号：EP0922944A2

    公开(公告)日：1999-06-16

    申请号：EP98830266.7

    申请日：1998-04-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Montanini, Pietro ,  Ferrera, Marco ,  Castoldi, Laura ,  Gelmi, Ilaria

    IPC: G01L9/00

    CPC classification number: B81C1/00476 ,  B81B2203/033 ,  B81C1/00801 ,  B81C2201/0177 ,  B81C2201/053 ,  G01C19/56 ,  G01P15/0802 ,  G01P15/097 ,  G01P15/125 ,  H01L21/76202 ,  H01L21/764

    Abstract: The method is based on the use of a silicon carbide mask for removing a sacrificial region. In case of manufacture of integrated semiconductor material structures, the following steps are performed: forming a sacrificial region (6) of silicon oxide on a substrate (1) of semiconductor material; growing a pseudo-epitaxial layer (8); forming an electronic circuit (10-13, 18); depositing a silicon carbide layer (21); defining photolithographycally the silicon carbon layer so as to form an etching mask (23) containing the topography of a microstructure (27) to be formed; with the etching mask (23), forming trenches (25) in the pseudo-epitaxial layer (8) as far as the sacrificial region (6) so as to laterally define the microstructure; and removing the sacrificial region (6) through the trenches (25).

    Abstract translation: 该方法基于使用碳化硅掩模去除牺牲区域。 在制造集成半导体材料结构的情况下，执行以下步骤：在半导体材料的衬底（1）上形成氧化硅的牺牲区域（6） 生长伪外延层（8）; 形成电子电路（10-13,18）; 沉积碳化硅层（21）; 定义光刻硅碳层以形成包含待形成的微结构（27）的形貌的蚀刻掩模（23） 利用蚀刻掩模（23），在伪外延层（8）中形成直至牺牲区域（6）的沟槽（25）以横向地限定微结构; 并通过沟槽（25）去除牺牲区域（6）。

    Method for manufacturing integrated devices including electromechanical microstructures, without residual stress
    4.
    发明公开
    Method for manufacturing integrated devices including electromechanical microstructures, without residual stress 有权
    一种用于生产具有机电微结构集成器件过程中，没有残余应力

    公开(公告)号：EP1028466A1

    公开(公告)日：2000-08-16

    申请号：EP99830068.5

    申请日：1999-02-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Ferrari, Paolo ,  Vigna, Benedetto ,  Montanini, Pietro ,  Castoldi, Laura ,  Ferrera, Marco

    IPC: H01L27/00 ,  G01P1/00

    CPC classification number: B81B3/0072 ,  B81B2203/033 ,  B81C1/00666 ,  B81C2201/017 ,  G01P15/0802 ,  G01P2015/0828

    Abstract: On a substrate (20) of semiconductor material, a sacrificial region (21) is formed and an epitaxial layer (25) is grown; then a stress release trench (31) is formed, surrounding an area (33) of the epitaxial layer (25), where an integrated electromechanical microstructure is to be formed; the wafer (28) is then heat treated, to release residual stress. Subsequently, the stress release trench (31) is filled with a sealing region (34) of dielectric material, and integrated components are formed. Finally, inside the area surrounded by the sealing region (34), a microstructure definition trench is formed, and the sacrificial region is removed, thus obtaining an integrated microstructure with zero residual stress.

    Abstract translation: 上的半导体材料的基片（20），牺牲区域（21）被形成和外延层（25）上生长; 外延层（25），其中，在集成式机电微观结构是将要形成的那么应力释放槽（31）形成，周边区域（33）; 晶片（28）进行热处理，以释放残余应力。 接着，应力释放槽（31）中填充有电介质材料制成的密封区域（34），和集成的部件而形成。 最后，通过密封区域（34）包围的区域内，微结构定义沟槽中形成，并且所述牺牲区域被去除，因此，与零张残余应力获得集成微结构。

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