公开(公告)号：EP4239960A1

公开(公告)日：2023-09-06

申请号：EP23156362.8

申请日：2023-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： MINNELLA, Filippo ,  DONZELLI, Gea

IPC: H04L25/02

Abstract: A processing system (10a) is described. The processing system (10a) comprises a UART communication interface (50) managing a transmission and a reception signal according to a given baud rate, and a baud-rate detection circuit (70).
Specifically, an edge detector (700) is configured to generate a first control signal (TRIG) indicating edges in the reception signal (RX). In response to an edge in the reception signal (RX), a digital counter circuit (702) resets a count value (CNT). Conversely, in the absence of edges, the digital counter circuit (702) increases the count value (CNT). Once a new edge is signaled, a validation circuit (704) verifies the count value (CNT). Specifically, when the count value (CNT) is smaller than a maximum value (MAX_CNT), the validation circuit (704) asserts a second control signal (SEL). Otherwise, the validation circuit (704) de-asserts the second control signal.
A register (706; 708) is configured to provide a threshold signal (BIT_CNT) by storing the count value (CNT) when the second control signal (SEL) is asserted. Accordingly, the count value (CNT) indicates the time between two consecutive edges of the reception signal, wherein the validation circuit updates the threshold signal (BIT_CNT) stored by the register only when this time is in a permitted range, e.g. , in order to update the register only in case the time corresponds presumably to the duration of a single bit. Accordingly, the baud rate of the UART communication interface (50) may be determined as a function of the threshold signal (BIT_CNT) stored by the register.

公开(公告)号：EP4145150A1

公开(公告)日：2023-03-08

申请号：EP22189096.5

申请日：2022-08-05

Applicant: STMicroelectronics S.r.l.

Inventor： CANNONE, Alessandro ,  FERRARA, Enrico ,  ERRICO, Nicola ,  DONZELLI, Gea

IPC: G01R31/3167 ,  G01R31/00 ,  G01R31/317 ,  G06F30/30 ,  B60W30/00

Abstract: Disclosed herein is a single integrated circuit chip including main logic (11) that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area (12') that operates to verify proper operation of the main logic (11). A checker circuit (16') within the chip outside of the safety area serves to verify proper operation of the checker circuit. The checker circuit (16') receives signals from the safety circuit and uses combinatorial logic circuit to verify from those signals that the check circuit is operating properly.

公开(公告)号：EP3996281A1

公开(公告)日：2022-05-11

申请号：EP21204292.3

申请日：2021-10-22

Applicant: STMicroelectronics S.r.l.

Inventor： ERRICO, Nicola ,  ANNOVAZZI, Marzia ,  CANNONE, Alessandro ,  FERRARA, Enrico ,  DONZELLI, Gea ,  TURBANTI, Paolo

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/12

Abstract: A circuit (100) for use in transmission control units and braking control units for motor vehicles comprises of plurality of N sensing channels such as BJT-based temperature sensing channels. Each channel includes a first main sensing node (S_CH_1 to S_CH_N) and a second redundancy sensing node (S_CH_1R to S_CH_NR) paired therewith. A plurality of N analog-to-digital converters (ADC_1 to ADC_N) are coupled to the first sensing nodes (S_CF_1 to S_CH_N), with digital processing circuitry (101, 102) coupled to the converters (ADC 1 to ADC N) and configured to perform, e.g. interpolator processing of the N first digital signals. A pair of multiplexers (MUX1, MUX2) are coupled to the second sensing nodes (S_CF_1R to S_CF_NR) and to the N analog-to-digital converters (ADC_1 to ADC_N), with a further analog-to-digital converter (ADC_R) coupled to the output of the second multiplexer (MUX2). Error checking circuitry (103) is coupled to the outputs of the second multiplexer (MUX2) and the further analog-to-digital converter (ADC_R) to compare, at each time window in the sequence of N time windows, a first digital value (TEMP _CODE) and a second digital value (TEMP_CODE_RED) resulting from conversion to digital of: an analog sensing signal at one of the first sensing nodes (S_CF_1 to S_CH_N), and an analog sensing signal at the second sensing paired with the selected one of the first sensing nodes (S_CF_1 to S_CH_N).