公开(公告)号：EP4270206A1

公开(公告)日：2023-11-01

申请号：EP23162258.0

申请日：2023-03-16

Applicant: STMicroelectronics S.r.l.

Inventor： OREGGIA, Daniele ,  CANNONE, Alessandro ,  ALAGNA, Diego ,  RAIMONDI, Marcello

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/40 ,  H04L12/40 ,  H01M10/42

Abstract: A battery management system includes: a controller (211); a master battery management integrated circuit, BMIC, device (213M) coupled to the controller (211) and configured to communicate with the controller (211) through a standard Serial Peripheral Interface, SPI, protocol; and a first slave BMIC device (213SA) and a second slave BMIC device (213SB) that are connected in a daisy chain configuration and communicating through Isolated SPI interfaces, where the first slave BMIC device (213 SA) is coupled to the master BMIC device (213M) through an Isolated SPI interface, where the Isolated SPI interface uses a differential signal comprising a positive signal and a complementary negative signal, where a bit frame of the positive signal includes a bit period followed by an idle period having a same duration as the bit period, where the first slave BMIC device (213SA) and the second slave BMIC device (213SB) are configured to be coupled to a first battery pack and a second battery pack, respectively.

公开(公告)号：EP4372396A1

公开(公告)日：2024-05-22

申请号：EP23206339.6

申请日：2023-10-27

Applicant: STMicroelectronics S.r.l.

Inventor： ERRICO, Nicola ,  CANNONE, Alessandro ,  FERRARA, Enrico ,  PISCITELLI, Luigi

IPC: G01R31/28 ,  G05B9/03

CPC classification number: G01R31/2829 ,  G05B9/03

Abstract: A circuit includes: first analog-to-digital converters, ADCs (105) configured to be coupled to respective ones of first sensors(101); a first multiplexer, MUX (111) coupled to output terminals of the first ADCs; a second MUX (109) configured to be coupled to second sensors (103) which are redundant sensors for the first sensors; a second ADC (107) coupled to an output terminal of the second MUX, the first MUX and the second MUX being controlled by a selection signal (108); a first checker circuit (133) configured to compare a first data at an output terminal of the first MUX with a second data at an output terminal of the second ADC; and a plurality of switches (155) coupled between respective ones of the input terminals of the second MUX and a reference voltage node(154).

公开(公告)号：EP4290254A1

公开(公告)日：2023-12-13

申请号：EP23174170.3

申请日：2023-05-18

Applicant: STMicroelectronics S.r.l.

Inventor： ALAGNA, Diego ,  CANNONE, Alessandro

IPC: G01R31/317

Abstract: Circuit arrangement for validation of operation of a logic module (11) in a multipower logic architecture (10), comprising
at least a first logic module (11) operating with a first clock signal (MCK) and a first power supply (VMP), and
a second logic module (12) operating with a second clock signal (SCK) and second power supply (VMP),
said first logic module (11) and second logic module (12) being configured to exchange signals at least on a communication link (DL), wherein
the first logic module (11) is configured to generate a first validation signal (A) and a second validation signal (B), in particular on a first and second wire respectively, which are sent over the communication link (DL) to the second logic module (12), the values of said first validation signal (A) and second validation signal (B) being never zero at the same time,
the second logic module (12) being configured to
perform a first check that the second validation signal (B) is always logic one when the first validation signal (A) is zero,
perform a second check that the first validation signal (A) is always logic one when the second validation signal (B) is zero,
perform a cyclic check that the first validation signal (A) and the second validation signal (B) are not stuck-at-1, and
to validate (MV) the operation of the first logic module (A) if said first check, second check and cyclic check give each a positive result.

公开(公告)号：EP4145150A1

公开(公告)日：2023-03-08

申请号：EP22189096.5

申请日：2022-08-05

Applicant: STMicroelectronics S.r.l.

Inventor： CANNONE, Alessandro ,  FERRARA, Enrico ,  ERRICO, Nicola ,  DONZELLI, Gea

IPC: G01R31/3167 ,  G01R31/00 ,  G01R31/317 ,  G06F30/30 ,  B60W30/00

Abstract: Disclosed herein is a single integrated circuit chip including main logic (11) that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area (12') that operates to verify proper operation of the main logic (11). A checker circuit (16') within the chip outside of the safety area serves to verify proper operation of the checker circuit. The checker circuit (16') receives signals from the safety circuit and uses combinatorial logic circuit to verify from those signals that the check circuit is operating properly.

公开(公告)号：EP3996281A1

公开(公告)日：2022-05-11

申请号：EP21204292.3

申请日：2021-10-22

Applicant: STMicroelectronics S.r.l.

Inventor： ERRICO, Nicola ,  ANNOVAZZI, Marzia ,  CANNONE, Alessandro ,  FERRARA, Enrico ,  DONZELLI, Gea ,  TURBANTI, Paolo

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/12

Abstract: A circuit (100) for use in transmission control units and braking control units for motor vehicles comprises of plurality of N sensing channels such as BJT-based temperature sensing channels. Each channel includes a first main sensing node (S_CH_1 to S_CH_N) and a second redundancy sensing node (S_CH_1R to S_CH_NR) paired therewith. A plurality of N analog-to-digital converters (ADC_1 to ADC_N) are coupled to the first sensing nodes (S_CF_1 to S_CH_N), with digital processing circuitry (101, 102) coupled to the converters (ADC 1 to ADC N) and configured to perform, e.g. interpolator processing of the N first digital signals. A pair of multiplexers (MUX1, MUX2) are coupled to the second sensing nodes (S_CF_1R to S_CF_NR) and to the N analog-to-digital converters (ADC_1 to ADC_N), with a further analog-to-digital converter (ADC_R) coupled to the output of the second multiplexer (MUX2). Error checking circuitry (103) is coupled to the outputs of the second multiplexer (MUX2) and the further analog-to-digital converter (ADC_R) to compare, at each time window in the sequence of N time windows, a first digital value (TEMP _CODE) and a second digital value (TEMP_CODE_RED) resulting from conversion to digital of: an analog sensing signal at one of the first sensing nodes (S_CF_1 to S_CH_N), and an analog sensing signal at the second sensing paired with the selected one of the first sensing nodes (S_CF_1 to S_CH_N).