公开(公告)号：EP4372396A1

公开(公告)日：2024-05-22

申请号：EP23206339.6

申请日：2023-10-27

Applicant: STMicroelectronics S.r.l.

Inventor： ERRICO, Nicola ,  CANNONE, Alessandro ,  FERRARA, Enrico ,  PISCITELLI, Luigi

IPC: G01R31/28 ,  G05B9/03

CPC classification number: G01R31/2829 ,  G05B9/03

Abstract: A circuit includes: first analog-to-digital converters, ADCs (105) configured to be coupled to respective ones of first sensors(101); a first multiplexer, MUX (111) coupled to output terminals of the first ADCs; a second MUX (109) configured to be coupled to second sensors (103) which are redundant sensors for the first sensors; a second ADC (107) coupled to an output terminal of the second MUX, the first MUX and the second MUX being controlled by a selection signal (108); a first checker circuit (133) configured to compare a first data at an output terminal of the first MUX with a second data at an output terminal of the second ADC; and a plurality of switches (155) coupled between respective ones of the input terminals of the second MUX and a reference voltage node(154).

公开(公告)号：EP4160350A1

公开(公告)日：2023-04-05

申请号：EP22192568.8

申请日：2022-08-29

Applicant: STMicroelectronics S.r.l.

Inventor： CIGNOLI, Marco ,  ERRICO, Nicola ,  VILMERCATI, Paolo ,  CASTORINA, Stefano ,  FERRARA, Enrico

IPC: G05F1/56 ,  H03K19/007

Abstract: Disclosed herein is a single integrated circuit chip with a main logic (11) that operates a vehicle component such as a valve driver. Isolated from the main logic (11) within the chip is a safety area (12') that operates to verify proper operation of the main logic. The safety area (12') is internally powered by an internal regulated voltage (VREG) generated by an internal voltage regulator that generates the internal regulated voltage from an external voltage (PWR_IN) while protecting against shorts of the external line delivering the external voltage. The safety area (12') includes protection circuits (25) that level shift external analog signals downward in voltage for monitoring within the safety area, the protection circuits (25) serving to protect against shorts of the external line delivering the external analog signals.

公开(公告)号：EP4145150A1

公开(公告)日：2023-03-08

申请号：EP22189096.5

申请日：2022-08-05

Applicant: STMicroelectronics S.r.l.

Inventor： CANNONE, Alessandro ,  FERRARA, Enrico ,  ERRICO, Nicola ,  DONZELLI, Gea

IPC: G01R31/3167 ,  G01R31/00 ,  G01R31/317 ,  G06F30/30 ,  B60W30/00

Abstract: Disclosed herein is a single integrated circuit chip including main logic (11) that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area (12') that operates to verify proper operation of the main logic (11). A checker circuit (16') within the chip outside of the safety area serves to verify proper operation of the checker circuit. The checker circuit (16') receives signals from the safety circuit and uses combinatorial logic circuit to verify from those signals that the check circuit is operating properly.

公开(公告)号：EP3996281A1

公开(公告)日：2022-05-11

申请号：EP21204292.3

申请日：2021-10-22

Applicant: STMicroelectronics S.r.l.

Inventor： ERRICO, Nicola ,  ANNOVAZZI, Marzia ,  CANNONE, Alessandro ,  FERRARA, Enrico ,  DONZELLI, Gea ,  TURBANTI, Paolo

IPC: H03M1/06 ,  H03M1/10 ,  H03M1/12

Abstract: A circuit (100) for use in transmission control units and braking control units for motor vehicles comprises of plurality of N sensing channels such as BJT-based temperature sensing channels. Each channel includes a first main sensing node (S_CH_1 to S_CH_N) and a second redundancy sensing node (S_CH_1R to S_CH_NR) paired therewith. A plurality of N analog-to-digital converters (ADC_1 to ADC_N) are coupled to the first sensing nodes (S_CF_1 to S_CH_N), with digital processing circuitry (101, 102) coupled to the converters (ADC 1 to ADC N) and configured to perform, e.g. interpolator processing of the N first digital signals. A pair of multiplexers (MUX1, MUX2) are coupled to the second sensing nodes (S_CF_1R to S_CF_NR) and to the N analog-to-digital converters (ADC_1 to ADC_N), with a further analog-to-digital converter (ADC_R) coupled to the output of the second multiplexer (MUX2). Error checking circuitry (103) is coupled to the outputs of the second multiplexer (MUX2) and the further analog-to-digital converter (ADC_R) to compare, at each time window in the sequence of N time windows, a first digital value (TEMP _CODE) and a second digital value (TEMP_CODE_RED) resulting from conversion to digital of: an analog sensing signal at one of the first sensing nodes (S_CF_1 to S_CH_N), and an analog sensing signal at the second sensing paired with the selected one of the first sensing nodes (S_CF_1 to S_CH_N).