公开(公告)号：EP1126614B1

公开(公告)日：2004-11-17

申请号：EP00830102.0

申请日：2000-02-14

Applicant: STMicroelectronics S.r.l.

Inventor： Ghezzi, Stefano ,  Ferrario, Donato ,  Yero, Emilio ,  Campardo, Giovanni

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17704 ,  H03K19/1778 ,  Y10T307/505

公开(公告)号：EP0928003B1

公开(公告)日：2005-09-21

申请号：EP98114061.9

申请日：1998-07-28

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Ferrario, Donato ,  Ghezzi, Stefano

IPC: G11C8/00 ,  G11C11/408

CPC classification number: G11C8/08 ,  G11C11/4085

公开(公告)号：EP0915478A1

公开(公告)日：1999-05-12

申请号：EP97830572.0

申请日：1997-11-05

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Ferrario, Donato ,  Golla, Carla Maria

IPC: G11C16/00 ,  G11C8/00 ,  G11C5/14

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C8/10

Abstract: A boosting circuit supplied by a first voltage level (Vcc) and a second voltage level (Gnd), and having an output line (13) capable of taking a third voltage level, characterized by comprising at least two distinct circuits (A1,11,A2,12) for generating said third voltage level, the at least two circuits selectively activatable for generating said third voltage level and selectively couplable to said output line (13).

Abstract translation: 由第一电压电平（Vcc）和第二电压电平（Gnd）提供的升压电路，并且具有能够获取第三电压电平的输出线（13），其特征在于包括至少两个不同的电路（A1,11， A2,12），用于产生所述第三电压电平，所述至少两个电路选择性地激活以产生所述第三电压电平并且可选择性地耦合到所述输出线（13）。

公开(公告)号：EP1126614A1

公开(公告)日：2001-08-22

申请号：EP00830102.0

申请日：2000-02-14

Applicant: STMicroelectronics S.r.l.

Inventor： Ghezzi, Stefano ,  Ferrario, Donato ,  Yero, Emilio ,  Campardo, Giovanni

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17704 ,  H03K19/1778 ,  Y10T307/505

Abstract: A programmable logic array (PLA) has at least an AND plane comprising an array of transistors arranged in rows and columns, the transistors belonging to a same column being connected in series with each other, the two end current terminals of said series of transistors being coupled to the supply voltage rail (VDD) and to a reference (GND), respectively, the transistors of the first row and of the last row of the array having their control terminals coupled to respective opposite enabling/disabling potentials. To each row of said array, with the exception of the first and the last row, are associated three control lines, the first line being coupled to a first input value, the second line being coupled to the inverted logic value of the first input value and the third line being coupled to a voltage sufficient to keep in a state of conduction the transistors of the row connected to it. Each transistor of each row except the first and the last row has its control terminal connected to one of the three control lines associated to the row.
An OR plane comprises at least an array of transistors arranged in rows and columns, the transistors belonging to a same column having their respective control terminals connected to a control line and a first current terminal coupled to a reference potential (GND), each transistor of each row of the array having a second current terminal connected or not to a respective output line. The second current terminal of each transistor of the array that is not connected to a respective output line is short-circuited to the first current terminal of the same transistor.

Abstract translation: 可编程逻辑阵列（PLA）具有至少一个AND平面，其包括以行和列排列的晶体管阵列，属于同一列的晶体管彼此串联连接，所述一系列晶体管的两个端电流端子 耦合到电源电压轨（VDD）和参考（GND），阵列的第一行和最后一行的晶体管的控制端分别耦合到相应的使能/禁止电位。 除了第一行和最后一行之外，对于所述阵列的每一行都关联三个控制线，第一行耦合到第一输入值，第二行耦合到第一输入值的反相逻辑值 并且第三线被耦合到足以保持处于与其连接的行的晶体管的导通状态的电压。 除了第一行和最后一行之外，每行的每个晶体管的控制端连接到与行相关联的三条控制线之一。 OR平面包括至少排列成行和列的晶体管阵列，属于相同列的晶体管的各自的控制端子连接到控制线和耦合到参考电位（GND）的第一电流端子，每个晶体管 阵列的每一行具有连接到或不连接到相应输出线的第二电流端子。 未连接到相应输出线的阵列的每个晶体管的第二电流端子与同一晶体管的第一电流端短路。

公开(公告)号：EP0928003A3

公开(公告)日：2000-01-12

申请号：EP98114061.9

申请日：1998-07-28

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Ferrario, Donato ,  Ghezzi, Stefano

IPC: G11C8/00 ,  G11C11/408

CPC classification number: G11C8/08 ,  G11C11/4085

Abstract: The invention relates to a row decoding circuit for an electronic memory cell device, particularly in low supply voltage applications, being of the type adapted to boost, through at least one boost capacitor (Cboost), a read voltage to be applied to a memory column containing a memory cell to be read. The circuit is powered between a first supply voltage reference (Vpcx) and a second ground potential reference (GND), and comprises a hierarchic structure (13) of cascade connected inverters (15,16) and a circuit means of progressively raising the read voltage level dynamically. First means (Cboost0,D1) are provided for raising the read voltage level to a value equal to the supply voltage (Vpcx) plus a threshold voltage (Vtp), and second means (Cboost1,D2) are provided for raising the read voltage level to a value equal to the supply voltage (Vpcx) plus twice said threshold voltage (Vtp).

公开(公告)号：EP0915476B1

公开(公告)日：2004-03-03

申请号：EP97830573.8

申请日：1997-11-05

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino ,  Zammattio, Matteo ,  Ferrario, Donato

IPC: G11C8/00 ,  G11C7/00

CPC classification number: G11C8/18

公开(公告)号：EP0928003A2

公开(公告)日：1999-07-07

申请号：EP98114061.9

申请日：1998-07-28

Applicant: STMicroelectronics S.r.l.

Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Ferrario, Donato ,  Ghezzi, Stefano

IPC: G11C8/00 ,  G11C11/408

CPC classification number: G11C8/08 ,  G11C11/4085

Abstract: The invention relates to a row decoding circuit for an electronic memory cell device, particularly in low supply voltage applications, being of the type adapted to boost, through at least one boost capacitor (Cboost), a read voltage to be applied to a memory column containing a memory cell to be read.
The circuit is powered between a first supply voltage reference (Vpcx) and a second ground potential reference (GND), and comprises a hierarchic structure (13) of cascade connected inverters (15,16) and a circuit means of progressively raising the read voltage level dynamically. First means (Cboost0,D1) are provided for raising the read voltage level to a value equal to the supply voltage (Vpcx) plus a threshold voltage (Vtp), and second means (Cboost1,D2) are provided for raising the read voltage level to a value equal to the supply voltage (Vpcx) plus twice said threshold voltage (Vtp).

Abstract translation: 本发明涉及一种用于电子存储单元装置的行解码电路，特别是在低电源电压应用中，其适用于通过至少一个升压电容器（Cboost）来升压要施加到存储器列的读取电压 包含要读取的存储单元。 电路在第一电源电压基准（Vpcx）和第二接地电位基准（GND）之间供电，并且包括级联连接的逆变器（15,16）的分级结构（13）和逐渐提高读取电压的电路装置 动态级别。 第一装置（Cboost0，D1）被提供用于将读取电压电平升高到等于电源电压（Vpcx）加上阈值电压（Vtp）的值，并且提供第二装置（Cboost1，D2）以提高读取电压电平 达到等于电源电压（Vpcx）加上两倍阈值电压（Vtp）的值。

公开(公告)号：EP0915476A1

公开(公告)日：1999-05-12

申请号：EP97830573.8

申请日：1997-11-05

Applicant: STMicroelectronics S.r.l.

Inventor： Campardo, Giovanni ,  Micheloni, Rino ,  Zammattio, Matteo ,  Ferrario, Donato

IPC: G11C8/00 ,  G11C7/00

CPC classification number: G11C8/18

Abstract: The invention relates to a method and a circuit for regulating a pulse synchronization signal (ATD) for the memory cell read phase in semiconductor integrated electronic memory devices. The pulse signal (ATD) is generated upon detection of a change in logic state of at least one of a plurality of address input terminals of the memory cells, so as to also generate an equalization signal (SAEQ) to a sense amplifier.
The SAEQ pulse is blocked (STOP) upon the row voltage reaching a predetermined sufficient value to provide reliable reading. Advantageously, the pulse blocking is produced by a logic signal (STOP) activated upon a predetermined voltage value being exceeded during the overboost phase of the addressed memory row.

Abstract translation: 本发明涉及一种用于调整半导体集成电子存储器件中存储单元读取相位的脉冲同步信号（ATD）的方法和电路。 在检测到存储单元的多个地址输入端中的至少一个的逻辑状态的变化时产生脉冲信号（ATD），以便也产生到读出放大器的均衡信号（SAEQ）。 当行电压达到预定的足够值时，SAEQ脉冲被阻塞（STOP），以提供可靠的读数。 有利地，通过在寻址的存储器行的过载阶段期间超过预定电压值而激活的逻辑信号（STOP）产生脉冲阻塞。