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    Row decoder circuit for an electronic memory device, particularly for low voltage application
    5.
    发明公开
    Row decoder circuit for an electronic memory device, particularly for low voltage application 失效
    Zeilendekodierschaltungfürelektronische Speicheranordnung，insbesonderefürniedrige Spannungspeisung

    公开(公告)号：EP0928003A2

    公开(公告)日：1999-07-07

    申请号：EP98114061.9

    申请日：1998-07-28

    Applicant: STMicroelectronics S.r.l.

    Inventor： Micheloni, Rino ,  Campardo, Giovanni ,  Ferrario, Donato ,  Ghezzi, Stefano

    IPC: G11C8/00 ,  G11C11/408

    CPC classification number: G11C8/08 ,  G11C11/4085

    Abstract: The invention relates to a row decoding circuit for an electronic memory cell device, particularly in low supply voltage applications, being of the type adapted to boost, through at least one boost capacitor (Cboost), a read voltage to be applied to a memory column containing a memory cell to be read.
    The circuit is powered between a first supply voltage reference (Vpcx) and a second ground potential reference (GND), and comprises a hierarchic structure (13) of cascade connected inverters (15,16) and a circuit means of progressively raising the read voltage level dynamically. First means (Cboost0,D1) are provided for raising the read voltage level to a value equal to the supply voltage (Vpcx) plus a threshold voltage (Vtp), and second means (Cboost1,D2) are provided for raising the read voltage level to a value equal to the supply voltage (Vpcx) plus twice said threshold voltage (Vtp).

    Abstract translation: 本发明涉及一种用于电子存储单元装置的行解码电路，特别是在低电源电压应用中，其适用于通过至少一个升压电容器（Cboost）来升压要施加到存储器列的读取电压 包含要读取的存储单元。 电路在第一电源电压基准（Vpcx）和第二接地电位基准（GND）之间供电，并且包括级联连接的逆变器（15,16）的分级结构（13）和逐渐提高读取电压的电路装置 动态级别。 第一装置（Cboost0，D1）被提供用于将读取电压电平升高到等于电源电压（Vpcx）加上阈值电压（Vtp）的值，并且提供第二装置（Cboost1，D2）以提高读取电压电平 达到等于电源电压（Vpcx）加上两倍阈值电压（Vtp）的值。

    Removable data storage device and related assembling method
    6.
    发明公开
    Removable data storage device and related assembling method 审中-公开
    Entfernbare Datenspeichervorrichtung undzugehörigesMontageverfahren

    公开(公告)号：EP1689217A1

    公开(公告)日：2006-08-09

    申请号：EP06001378.6

    申请日：2006-01-24

    Applicant: STMicroelectronics S.r.l.

    Inventor： Roveda, Marco ,  Villa, Davide ,  Zonca, Romina ,  Ghezzi, Stefano ,  Saltutti, Stefano ,  Costanzo, Luigi

    IPC: H05K5/02

    CPC classification number: H05K5/026

    Abstract: A removable storage device is described comprising at least one substrate (1) whereon a plurality of components (2, 3) are arranged. Advantageously, the removable storage device (10) comprises a casing (4) of the package type suitable to completely cover these components (2, 3) and to form, together with the substrate (1), an external coating of the removable storage device (10).
    Moreover, a method is described for assembling at least one removable storage device (10) thus realised.

    Abstract translation: 描述了一种可移动存储装置，其包括布置有多个部件（2,3）的至少一个基板（1）。 有利地，可移除存储装置（10）包括适合于完全覆盖这些部件（2,3）并与衬底（1）一起形成可拆卸存储装置的外部涂层的封装类型的壳体（4） （10）。 此外，描述了用于组装由此实现的至少一个可移动存储设备（10）的方法。

    Memory circuit with improved address signal generator
    9.
    发明公开
    Memory circuit with improved address signal generator 失效
    Speicherschaltung mit verbicultem Adressensignalgenerator

    公开(公告)号：EP0913829A1

    公开(公告)日：1999-05-06

    申请号：EP97830558.9

    申请日：1997-10-31

    Applicant: STMicroelectronics S.r.l.

    Inventor： Campardo, Giovanni ,  Commodaro, Stefano ,  Ghezzi, Stefano ,  Maccarrone, Marco

    IPC: G11C8/04 ,  G11C16/06

    CPC classification number: G11C16/16 ,  G11C8/04

    Abstract: The present invention relates to a semiconductor memory device with an improved address signal generator. The memory device comprises an array of memory elements (10), first decoding circuit means (8,15) for decoding a first set of address signals (7,14) for the selection of said memory elements, and second circuit means (4) for the generation internally to the memory of a sequence of values for said address signals (3,11). The second circuit means (4) generates said sequence so that successive values in the sequence differ for the logic state of only one of said address signals (3,11).

    Abstract translation: 本发明涉及具有改进的地址信号发生器的半导体存储器件。 存储器件包括存储元件阵列（10），第一解码电路装置（8,15），用于对用于选择所述存储器元件的第一组地址信号（7,14）进行解码;以及第二电路装置（4） 用于内部生成用于所述地址信号（3,11）的一系列值的存储。 第二电路装置（4）产生所述序列，使得序列中的连续值对于仅一个所述地址信号（3,11）的逻辑状态不同。

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