公开(公告)号：EP1126614B1

公开(公告)日：2004-11-17

申请号：EP00830102.0

申请日：2000-02-14

Applicant: STMicroelectronics S.r.l.

Inventor： Ghezzi, Stefano ,  Ferrario, Donato ,  Yero, Emilio ,  Campardo, Giovanni

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17704 ,  H03K19/1778 ,  Y10T307/505

公开(公告)号：EP1126614A1

公开(公告)日：2001-08-22

申请号：EP00830102.0

申请日：2000-02-14

Applicant: STMicroelectronics S.r.l.

Inventor： Ghezzi, Stefano ,  Ferrario, Donato ,  Yero, Emilio ,  Campardo, Giovanni

IPC: H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/17704 ,  H03K19/1778 ,  Y10T307/505

Abstract: A programmable logic array (PLA) has at least an AND plane comprising an array of transistors arranged in rows and columns, the transistors belonging to a same column being connected in series with each other, the two end current terminals of said series of transistors being coupled to the supply voltage rail (VDD) and to a reference (GND), respectively, the transistors of the first row and of the last row of the array having their control terminals coupled to respective opposite enabling/disabling potentials. To each row of said array, with the exception of the first and the last row, are associated three control lines, the first line being coupled to a first input value, the second line being coupled to the inverted logic value of the first input value and the third line being coupled to a voltage sufficient to keep in a state of conduction the transistors of the row connected to it. Each transistor of each row except the first and the last row has its control terminal connected to one of the three control lines associated to the row.
An OR plane comprises at least an array of transistors arranged in rows and columns, the transistors belonging to a same column having their respective control terminals connected to a control line and a first current terminal coupled to a reference potential (GND), each transistor of each row of the array having a second current terminal connected or not to a respective output line. The second current terminal of each transistor of the array that is not connected to a respective output line is short-circuited to the first current terminal of the same transistor.

Abstract translation: 可编程逻辑阵列（PLA）具有至少一个AND平面，其包括以行和列排列的晶体管阵列，属于同一列的晶体管彼此串联连接，所述一系列晶体管的两个端电流端子 耦合到电源电压轨（VDD）和参考（GND），阵列的第一行和最后一行的晶体管的控制端分别耦合到相应的使能/禁止电位。 除了第一行和最后一行之外，对于所述阵列的每一行都关联三个控制线，第一行耦合到第一输入值，第二行耦合到第一输入值的反相逻辑值 并且第三线被耦合到足以保持处于与其连接的行的晶体管的导通状态的电压。 除了第一行和最后一行之外，每行的每个晶体管的控制端连接到与行相关联的三条控制线之一。 OR平面包括至少排列成行和列的晶体管阵列，属于相同列的晶体管的各自的控制端子连接到控制线和耦合到参考电位（GND）的第一电流端子，每个晶体管 阵列的每一行具有连接到或不连接到相应输出线的第二电流端子。 未连接到相应输出线的阵列的每个晶体管的第二电流端子与同一晶体管的第一电流端短路。

公开(公告)号：EP1126372B1

公开(公告)日：2005-05-18

申请号：EP00830103.8

申请日：2000-02-14

Applicant: STMicroelectronics S.r.l.

Inventor： Manstretta, Alessandro ,  Micheloni, Rino ,  Pierin, Andrea ,  Yero, Emilio

IPC: G06F11/20

CPC classification number: G11C29/70

公开(公告)号：EP1126372A1

公开(公告)日：2001-08-22

申请号：EP00830103.8

申请日：2000-02-14

Applicant: STMicroelectronics S.r.l.

Inventor： Manstretta, Alessandro ,  Micheloni, Rino ,  Pierin, Andrea ,  Yero, Emilio

IPC: G06F11/20

CPC classification number: G11C29/70

Abstract: This invention relates to a non-volatile memory device (20) with configurable row redundancy, comprising:

a non-volatile memory (11) comprising of at least one matrix (11') of memory cells and at least one matrix (11") of redundant memory cells, both organised into rows and columns;
row and column decoding circuits (12,13);
read and modify circuits for reading and modifying data stored in the memory cells; and
at least one associative memory matrix (14), also organised into rows and columns, able to store the addresses of faulty rows, and control circuits for controlling the associative memory matrix.

The memory device (20) of this invention further comprises:

at least one circuit for recognising and comparing selected row addresses (ADr) with faulty row addresses (ADrr) contained in the associative memory matrix (14), such as to produce de-selection of the faulty row and selection of the corresponding redundant cell row in the event of a valid recognition; and
at least one configuration register (17), also comprising a matrix of non-volatile memory cells, and associated control circuits.

Abstract translation: 本发明涉及一种具有可配置行冗余性的非易失性存储器件（20），包括：非易失性存储器（11），包括至少一个存储器单元矩阵（11'）和至少一个矩阵（11“）， 冗余存储器单元，被组织成行和列;行和列解码电路（12,13）;用于读取和修改存储在存储器单元中的数据的读取和修改电路;以及至少一个关联存储器矩阵（14） 本发明的存储器件（20）还包括：用于识别和比较所选行地址（ADr）的至少一个电路 ），包括在所述关联存储器矩阵（14）中的有缺陷的行地址（ADrr），以便在有效识别的情况下产生故障行的选择和对应的冗余单元行的选择;以及至少一个配置 （17），还包括非易失性存储器单元矩阵和相关联的控制电路。