公开(公告)号：EP0899878B1

公开(公告)日：2003-11-05

申请号：EP97830432.7

申请日：1997-08-29

Applicant: STMicroelectronics S.r.l.

Inventor： Rossi, Annamaria ,  Fucili, Giona ,  Cane, Marcello ,  Nessi, Maurizio

IPC: H03K3/00 ,  H03K3/356 ,  H03K3/037

CPC classification number: H03K3/037 ,  H03K3/356113

公开(公告)号：EP1241670B1

公开(公告)日：2006-06-21

申请号：EP01830176.2

申请日：2001-03-15

Applicant: STMicroelectronics S.r.l.

Inventor： Schillaci, Luca ,  Nessi, Maurizio ,  Galbiati, Ezio

IPC: G11B21/08 ,  G11B5/55

CPC classification number: G11B5/5547 ,  G11B21/083

公开(公告)号：EP0899878A1

公开(公告)日：1999-03-03

申请号：EP97830432.7

申请日：1997-08-29

Applicant: STMicroelectronics S.r.l.

Inventor： Rossi, Annamaria ,  Fucili, Giona ,  Cane, Marcello ,  Nessi, Maurizio

IPC: H03K3/00 ,  H03K3/356 ,  H03K3/037

CPC classification number: H03K3/037 ,  H03K3/356113

Abstract: A toggle flip-flop (FFT) with reduced integration area, comprising a flip-flop of the D type with an inverting input stage (T,A,B,C) and a master-slave portion.
Three transistors (M 1 ,M 2 ,M 3 ) connected to the inverting stage form a logic gate of the XOR type whereto the output terminal (Q) of the master-slave portion is fed back.

Abstract translation: 具有减小的积分区域的切换触发器（FFT）包括具有反相输入级（T，A，B，C）的D型触发器和主从部分。 连接到反相级的三个晶体管（M1，M2，M3）形成XOR类型的逻辑门，对主从部分的输出端（Q）进行反馈。

公开(公告)号：EP1207618B1

公开(公告)日：2005-10-05

申请号：EP00830764.7

申请日：2000-11-20

Applicant: STMicroelectronics S.r.l.

Inventor： Galbiati, Ezio ,  Nessi, Maurizio ,  Schillaci, Luca

IPC: H02P7/00

CPC classification number: H02P25/034

公开(公告)号：EP1137162B1

公开(公告)日：2005-02-16

申请号：EP00830225.9

申请日：2000-03-23

Applicant: STMicroelectronics S.r.l.

Inventor： Galbiati, Ezio ,  Nessi, Maurizio ,  Palestra, Marco

IPC: H02M7/5387

CPC classification number: H02M7/53873

公开(公告)号：EP1207618A1

公开(公告)日：2002-05-22

申请号：EP00830764.7

申请日：2000-11-20

Applicant: STMicroelectronics S.r.l.

Inventor： Galbiati, Ezio ,  Nessi, Maurizio ,  Schillaci, Luca

IPC: H02P7/00

CPC classification number: H02P25/034

Abstract: The present invention concerns a circuit for the speed recovery of a direct current motor comprising an output stage (1), consisting of a first couple of transistors (MOS1, MOS2) and of a second couple of transistors (MOS3, MOS4), and first means (5) for detecting a current circulating (Ivcm) in said motor. The inventive circuit has the characteristic of. comprising second means (7) suitable for activating said second couple of transistors (MOS3, MOS4) of said output stage (1) for a determined first time period (Tbrk) so as to short-circuit said motor (2), and at the end of said first time period (Tbrk) said second means (7) being suitable for unbalancing said output stage (1) so as to force the maximum current circulating (Ivcm) for a determined second time period (Tact) in function of the value detected by said first means (5) during said first time period (Tbrk) so as to stop said motor (2) in the shortest time possible.

Abstract translation: 本发明涉及一种用于包括输出级（1）组成的第一对晶体管（MOS 1，MOS 2）中的直流电动机的速度恢复的电路和第二对晶体管（MOS3，MOS4），和第一 装置（5）用于检测电流在所述电动机中循环（IVCM）。 根据本发明的电路具有的特性。 包括第二装置（7）适于启动所述输出级的所述第二对晶体管（MOS3，MOS4）（1）对于一个确定的开采第一时间段（Tbrk），以便短路所述电动机（2），并在 所述第一时间段（Tbrk）的端部，所述第二装置（7）适于不平衡所述输出级（1），以便迫使最大电流值的功能循环（IVCM），用于确定性开采第二时间段（轻触） 在所述第一时段（Tbrk）的第一装置（5）由所述检测到的，以便停止所述电动机（2）在最短的时间内。

公开(公告)号：EP0889598A1

公开(公告)日：1999-01-07

申请号：EP97830326.1

申请日：1997-06-30

Applicant: STMicroelectronics S.r.l.

Inventor： Rossi, Annamari ,  Fucili, Giona ,  Cane, Marcello ,  Nessi, Maurizio

IPC: H03M1/38

CPC classification number: H03M1/462

Abstract: A successive approximation register having a serial input (CM) and output (DO) comprises a chain of logic circuits of the bistable type which have selectable input terminals (FF4,FF3,FF2,FF1) feedback connected by a storage and control element (FF-s) and logic gate circuits (OR1,OR2,OR3) of the OR type, and connected to a serial line through respective internal switches (TG1) communicating the serial line to input terminals (S) of the logic circuits in said chain, the serial line forming an input to a flip-flop (FFD) of the D type which is the output element of the register.

Abstract translation: 具有串行输入（CM）和输出（DO）的逐次逼近寄存器包括具有由存储和控制元件（FF）连接的可选输入端（FF4，FF3，FF2，FF1）反馈的双稳态类型的逻辑电路链 -s）和逻辑门电路（OR1，OR2，OR3），并且通过将串行线路传送到所述链路中的逻辑电路的输入端子（S）的相应内部开关（TG1）连接到串行线路， 该串行线形成作为寄存器的输出元件的D型触发器（FFD）的输入。

公开(公告)号：EP1589651A1

公开(公告)日：2005-10-26

申请号：EP04425282.3

申请日：2004-04-23

Applicant: STMicroelectronics S.r.l.

Inventor： Nessi, Maurizio ,  Galbiati, Ezio

IPC: H02P1/00

CPC classification number: H02H9/047 ,  H02H7/0833

Abstract: The following invention refers to an apparatus for powering at least one electric motor (4, 6). The apparatus (100, 101) comprises at least one driving device (3, 5) of the electric motor (4, 6), a power circuit path (7) positioned between a generator (2) of power voltage (VCV) and the at least one driving device (3, 5), first means (8) inserted in the power circuit path (7) for enabling and preventing the powering of the at least one driving device (3, 5), a control device (10) powered by the feeding voltage (VCV) and suitable for controlling at least the first means (8). The apparatus (100, 101) comprises a protection device against the overvoltages (50, 60) comprising second means (COMP1, Q1) suitable for detecting a current that flows in the power circuit path (7) from the at least one driving device (3, 5) to the generator (2) of power voltage (VCV) and third means (Q2, OPAMP1) suitable ford absorbing the current detected (Iclamp).

Abstract translation: 以下发明涉及一种为至少一个电动机（4,6）供电的装置。 所述设备（100,101）包括所述电动机（4,6）的至少一个驱动装置（3,5），位于电源电压（VCV）的发电机（2）和所述电动机 至少一个驱动装置（3,5），插入所述电源电路路径（7）中的第一装置（8），用于启用和防止所述至少一个驱动装置（3,5）的供电，控制装置（10） 由供电电压（VCV）供电并且适于至少控制第一装置（8）。 装置（100,101）包括抵抗过电压（50,60）的保护装置，该保护装置包括适于检测来自至少一个驱动装置（7）在电力电路路径（7）中流动的电流的第二装置（COMP1，Q1） （VCV）的发生器（2）和适于吸收检测到的电流（Iclamp）的第三装置（Q2，OPAMP1）。

公开(公告)号：EP1241670A1

公开(公告)日：2002-09-18

申请号：EP01830176.2

申请日：2001-03-15

Applicant: STMicroelectronics S.r.l.

Inventor： Schillaci, Luca ,  Nessi, Maurizio ,  Galbiati, Ezio

IPC: G11B21/08 ,  G11B5/55

CPC classification number: G11B5/5547 ,  G11B21/083

Abstract: A circuit for estimating the speed of an electromagnetic actuator (VCM) associated with a reading head of a disc storage unit with a digital controller (15) comprises a resistor (Rs) in series with the actuator and an adder (30) with inputs connected to the supply terminals (P, M) of the actuator and to the measuring resistor (Rs) via means for transferring to the adder, in predetermined proportions and with predetermined sign, the supply voltage and the voltage across the measuring resistor (Rs). The transfer means comprising calibration means controlled by the controller (15) in order to determine the predetermined voltage proportions in a manner such that the output voltage of the circuit is substantially proportional to the back electromotive force generated by the actuator in motion. In order to achieve precision and versatility without occupying much integrated-circuit area, the calibration means comprise an adjustable-gain amplifier (34) and means for determining the gain of the amplifier, comprising coarse setting means (Vref2, 41, 42) and fine calibration means controlled by the controller.

Abstract translation: 用于利用数字控制器（15）估计与盘存储单元的读取头相关联的电磁致动器（VCM）的速度的电路包括与致动器串联的电阻器（Rs）和与输入相连的加法器（30） 通过用于以预定比例和预定的符号将测量电阻器（Rs）两端的电源电压和电压传送到加法器的装置，经由致动器的供电端子（P，M）和测量电阻器（Rs）。 传送装置包括由控制器（15）控制的校准装置，以便以使得电路的输出电压基本上与由致动器运动产生的反电动势成比例的方式确定预定的电压比例。 为了在不占用大量集成电路面积的情况下实现精确度和通用性，校准装置包括可调增益放大器（34）和用于确定放大器增益的装置，包括粗设置装置（Vref2,41,42）和精细 校准装置由控制器控制。

公开(公告)号：EP1137162A1

公开(公告)日：2001-09-26

申请号：EP00830225.9

申请日：2000-03-23

Applicant: STMicroelectronics S.r.l.

Inventor： Galbiati, Ezio ,  Nessi, Maurizio ,  Palestra, Marco

IPC: H02M7/5387

CPC classification number: H02M7/53873

Abstract: A feedback control circuit of the current in a load constituted by a winding in series to a current sensing resistor, coupled to a full-bridge output stage, an amplifier (SENSE_AMPL) coupled to the terminals of the sensing resistor, a controller fed with the output of the amplifier and with a voltage reference (V IN ) and producing a correction signal, has a PWM converter for generating a pair of control signals (I N +, I N -) that comprises an up/down counter producing a count value and a logic circuitry that produces the complement to two of the correction signal. A pair of registers first (D_I N +) and second (D_I N -) are coupled to the outputs of the controller and of the logic circuitry. A first comparator (COMP_1) coupled to the outputs of the counter and of the first register (D_I N +) produces the first control signal (I N +) if the count signal exceeds the value stored in the first register (D_I N +) and a second comparator (COMP_2) coupled to the counter and to the second register (D_I N -), produces the second control signal (I N -) if the count signal overcomes the value stored in the second register (D_I N -).

Abstract translation: 负载中的电流的反馈控制电路由串联连接到电流检测电阻器的绕组构成，耦合到全桥输出级，耦合到感测电阻器的端子的放大器（SENSE_AMPL），馈送有 具有用于产生一对控制信号（IN +，IN-）的PWM转换器，所述PWM转换器包括放大器的输出和参考电压（VIN）并产生校正信号，所述控制信号包括产生计数值的上/下计数器和逻辑电路 其产生对两个校正信号的补码。 一对寄存器（D_IN +）和第二（D_IN-）被耦合到控制器和逻辑电路的输出。 如果计数信号超过存储在第一寄存器（D_IN +）中的值和第二比较器（COMP_2），则耦合到计数器和第一寄存器（D_IN +）的输出的第一比较器（COMP_1）产生第一控制信号 ），如果计数信号克服存储在第二寄存器（D_IN-）中的值，则产生第二控制信号（IN-）到计数器和第二寄存器（D_IN-）。