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    INTEGRATED MAGNETORESISTIVE SENSOR, IN PARTICULAR THREE-AXES MAGNETORESISTIVE SENSOR AND MANUFACTURING METHOD THEREOF
    2.
    发明申请
    INTEGRATED MAGNETORESISTIVE SENSOR, IN PARTICULAR THREE-AXES MAGNETORESISTIVE SENSOR AND MANUFACTURING METHOD THEREOF 审中-公开
    集成磁传感器，特别是三轴磁阻传感器及其制造方法

    公开(公告)号：WO2012085296A1

    公开(公告)日：2012-06-28

    申请号：PCT/EP2011/074045

    申请日：2011-12-23

    Applicant: STMICROELECTRONICS S.R.L. ,  PACI, Dario ,  MORELLI, Marco ,  RIVA, Caterina

    Inventor： PACI, Dario ,  MORELLI, Marco ,  RIVA, Caterina

    IPC: G01R33/00 ,  G01R33/09

    CPC classification number: G01R33/0011 ,  B82Y25/00 ,  G01R33/093 ,  H01L43/12

    Abstract: An integrated magnetoresistive device, where a substrate (17) of semiconductor material is covered, on a first surface (19), by an insulating layer (18). A magnetoresistor (26) of ferromagnetic material extends in the insulating layer and defines a sensitivity plane of the sensor. A concentrator (34) of ferromagnetic material including at least one arm (34a), extending in a transversal direction to the sensitivity plane and vertically offset to the magnetoresistor (26). In this way, magnetic flux lines directed perpendicularly to the sensitivity plane are concentrated and deflected so as to generate magnetic-field components directed in a parallel direction to the sensitivity plane.

    Abstract translation: 通过绝缘层（18）在第一表面（19）上覆盖半导体材料的衬底（17）的集成磁阻器件。 铁磁材料的磁阻（26）在绝缘层中延伸并限定传感器的灵敏度平面。 铁磁材料的集中器（34）包括至少一个臂（34a），沿着横向方向延伸到灵敏度平面并垂直偏移到磁电阻（26）。 以这种方式，垂直于灵敏度平面指向的磁通线被集中和偏转，以便产生指向与灵敏平面平行的方向的磁场分量。

    PROCESS FOR MANUFACTURING AN INTERACTION STRUCTURE FOR A STORAGE MEDIUM
    3.
    发明申请
    PROCESS FOR MANUFACTURING AN INTERACTION STRUCTURE FOR A STORAGE MEDIUM 审中-公开
    用于制造存储介质的交互结构的过程

    公开(公告)号：WO2007113878A1

    公开(公告)日：2007-10-11

    申请号：PCT/IT2006/000229

    申请日：2006-04-06

    Applicant: STMICROELECTRONICS S.R.L. ,  RIVA, Caterina ,  MURARI, Bruno ,  FRATTINI, Giovanni

    Inventor： RIVA, Caterina ,  MURARI, Bruno ,  FRATTINI, Giovanni

    IPC: G11B9/00

    CPC classification number: G11B9/1409 ,  B82Y10/00 ,  G11B9/14

    Abstract: Described herein is a process for manufacturing an interaction structure for a storage medium, which envisages forming a first interaction head provided with a first conductive region having a sub-lithographic smaller dimension (W 1 ). The step of forming a first interaction head (7) envisages: forming on a surface (14) a first delimitation region (15) having a side wall; depositing a conductive portion (16b) having a deposition thickness substantially matching the sub- lithographic smaller dimension (W 1 ) on the side wall; and then defining the conductive portion. The sub- lithographic smaller dimension (W 1 ) is between 1 and 50 nm, preferably 20 nm.

    Abstract translation: 这里描述的是用于制造用于存储介质（4）的相互作用结构（6）的方法，其设想形成具有第二导电区域（22）的第一相互作用头部（7），所述第一导电区域具有次光刻尺寸较小（Wi） 。 形成第一相互作用头（7）的步骤设想：在表面（14）上形成具有侧壁（15b）的第一限定区域（15）; 在所述侧壁（15b）上沉积具有基本上与所述亚光刻较小尺寸（Wi）匹配的沉积厚度的导电部分（16b）; 然后限定导电部分。 亚光刻尺寸较小（Wi）在1至50nm之间，优选20nm。

    SUBSTRATE-LEVEL ASSEMBLY FOR AN INTEGRATED DEVICE, MANUFACTURING PROCESS THEREOF AND RELATED INTEGRATED DEVICE
    5.
    发明公开
    SUBSTRATE-LEVEL ASSEMBLY FOR AN INTEGRATED DEVICE, MANUFACTURING PROCESS THEREOF AND RELATED INTEGRATED DEVICE 审中-公开
    基板垫圈组合为一体的综合组成部分，用于生产及相关集成组件

    公开(公告)号：EP1945561A2

    公开(公告)日：2008-07-23

    申请号：EP06777802.7

    申请日：2006-07-14

    Applicant: STMicroelectronics S.r.l.

    Inventor： COMBI, Chantal ,  VIGNA, Benedetto ,  ZIGLIOLI, Federico Giovanni ,  BALDO, Lorenzo ,  MAGUGLIANI, Manuela ,  LASALANDRA, Ernesto ,  RIVA, Caterina

    IPC: B81B7/02

    CPC classification number: B81B7/0061 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0264 ,  B81C1/0023 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/1461 ,  H01L2924/3025 ,  H04R1/04 ,  H04R19/005 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A substrate-level assembly having a device substrate of semiconductor material with a top face and housing a first integrated device, including a buried cavity formed within the device substrate, and with a membrane suspended over the buried cavity in the proximity of the top face. A capping substrate is coupled to the device substrate above the top face so as to cover the first integrated device in such a manner that a first empty space is provided above the membrane. Electrical-contact elements electrically connect the integrated device with the outside of the substrate-level assembly. In one embodiment, the device substrate integrates at least a further integrated device provided with a respective membrane, and a further empty space, fluidly isolated from the first empty space, is provided over the respective membrane of the further integrated device.

    Abstract translation: 具有A衬底级组件的半导体材料的器件衬底具有顶面和外壳的第一集成器件，包括器件衬底内形成的掩埋空腔，并用悬浮在在顶面的接近掩埋空腔的膜。 甲封盖衬底耦合到所述顶面之上的器件衬底，以便覆盖所述第一集成器件在寻求做的膜上方提供第一空白空间的方式。 电接触元件电连接与所述衬底级组件的外部集成器件。 在一个实施例中，器件衬底至少集成设置有respectivement膜的进一步集成器件，和另外的空的空间，从所述第一空的空间流体地隔离，则在进一步的集成器件的respectivement膜提供。

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