公开(公告)号：US20160306765A1

公开(公告)日：2016-10-20

申请号：US14689677

申请日：2015-04-17

Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.

Inventor： Darrin C. Miller ,  Peter J. Meier ,  Gilbert Yoh

IPC: G06F13/40 ,  G06F1/08 ,  G06F13/42

CPC classification number: G06F13/4027 ,  G06F1/08 ,  G06F3/0656 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4059 ,  G06F13/4282 ,  G11C2207/107 ,  H03M2201/526 ,  Y02D10/14 ,  Y02D10/151

Abstract: A Serializer/Deserializer (SerDes) is described with an architecture that simultaneously provides flexibility for many different gear ratios as well as reduced power consumption. The SerDes utilizes latches where flops were previously used to help reduce power consumption, among other things. The SerDes also includes a main register bank with a plurality of sub-banks that can be filled according to any number of different schemes, thereby enabling the SerDes to accommodate different output widths.

Abstract translation: 串行器/解串器（SerDes）被描述为具有同时为许多不同传动比提供灵活性以及降低的功率消耗的架构。 SerDes利用锁存器，其中之前使用过翻牌来帮助降低功耗。 SerDes还包括具有可以根据任何数量的不同方案填充的多个子库的主寄存器组，从而使得SerDes能够适应不同的输出宽度。

公开(公告)号：US09767062B2

公开(公告)日：2017-09-19

申请号：US14689677

申请日：2015-04-17

Applicant: Avago Technologies General IP (Singapore) Pte. Ltd.

Inventor： Darrin C. Miller ,  Peter J. Meier ,  Gilbert Yoh

IPC: G06F13/40 ,  G06F13/42 ,  G06F1/08 ,  G06F3/06 ,  G06F13/38

CPC classification number: G06F13/4027 ,  G06F1/08 ,  G06F3/0656 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4059 ,  G06F13/4282 ,  G11C2207/107 ,  H03M2201/526 ,  Y02D10/14 ,  Y02D10/151

Abstract: A Serializer/Deserializer (SerDes) is described with an architecture that simultaneously provides flexibility for many different gear ratios as well as reduced power consumption. The SerDes utilizes latches where flops were previously used to help reduce power consumption, among other things. The SerDes also includes a main register bank with a plurality of sub-banks that can be filled according to any number of different schemes, thereby enabling the SerDes to accommodate different output widths.

公开(公告)号：US4862170A

公开(公告)日：1989-08-29

申请号：US171812

申请日：1988-03-22

Applicant: Youichi Hashimoto ,  Takashi Tokuyama ,  Kazuya Nishiga ,  Yoshihiro Arai ,  Nobuhide Ueki ,  Naoki Adachi

Inventor： Youichi Hashimoto ,  Takashi Tokuyama ,  Kazuya Nishiga ,  Yoshihiro Arai ,  Nobuhide Ueki ,  Naoki Adachi

IPC: G11B20/10 ,  H03M1/00 ,  H03M1/66

CPC classification number: H03M1/00 ,  H03M2201/03 ,  H03M2201/196 ,  H03M2201/30 ,  H03M2201/4212 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/526 ,  H03M2201/6121 ,  H03M2201/721

Abstract: A digital analog converter which is especially suitable for use in converting a digital audio signal into an analog audio signal includes a unit pulse response signal generator for successively generating unit pulse response signals at a predetermined time interval, a digital data generator for generating digital data at the predetermined time interval, a multiplier for multiplying a unit pulse response signal generated at a certain time by a predetermined item of the digital data, and a mixer for producing an analog signal output by combining the unit pulse response signals that have been multiplied by the digital data.

Abstract translation: 特别适用于将数字音频信号转换为模拟音频信号的数字模拟转换器包括用于以预定的时间间隔连续产生单位脉冲响应信号的单位脉冲响应信号发生器，用于产生数字数据的数字数据发生器 所述预定时间间隔，用于将在某一时间产生的单位脉冲响应信号乘以数字数据的预定项目的乘法器和用于产生模拟信号的混频器，所述混频器通过将已经乘以所述单位脉冲响应信号 数字数据。