公开(公告)号：US4010422A

公开(公告)日：1977-03-01

申请号：US409425

申请日：1973-10-25

Applicant: Kornelis Jan Wouda

Inventor： Kornelis Jan Wouda

IPC: H03M1/00 ,  H04B14/04 ,  H04B1/04

CPC classification number: H04B14/04 ,  H03M1/00 ,  H04B14/048 ,  H03M2201/01 ,  H03M2201/14 ,  H03M2201/16 ,  H03M2201/196 ,  H03M2201/2344 ,  H03M2201/4105 ,  H03M2201/4135 ,  H03M2201/4204 ,  H03M2201/4212 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/425 ,  H03M2201/4262 ,  H03M2201/52 ,  H03M2201/523 ,  H03M2201/534 ,  H03M2201/60 ,  H03M2201/6121 ,  H03M2201/712 ,  H03M2201/715 ,  H03M2201/8124

Abstract: A non-linear pulse code modulator wherein input signals are coded into digital representations of amplitude range segments and amplitude in excess of the minimum amplitude within the respective range segment uses a first analog-to-digital converter having a sawtooth-shaped control characteristic to determine the amplitude range segment from an input signal sample. The output of the first analog-to-digital converter is used to effectively divide the signal sample by a factor 2.sup.n, where n corresponds to the determined range. The result of the division is then converted in a second analog-to-digital conversion to a digital signal that is combined with the digital range segment signal for transmission thereof.

公开(公告)号：US4862170A

公开(公告)日：1989-08-29

申请号：US171812

申请日：1988-03-22

Applicant: Youichi Hashimoto ,  Takashi Tokuyama ,  Kazuya Nishiga ,  Yoshihiro Arai ,  Nobuhide Ueki ,  Naoki Adachi

Inventor： Youichi Hashimoto ,  Takashi Tokuyama ,  Kazuya Nishiga ,  Yoshihiro Arai ,  Nobuhide Ueki ,  Naoki Adachi

IPC: G11B20/10 ,  H03M1/00 ,  H03M1/66

CPC classification number: H03M1/00 ,  H03M2201/03 ,  H03M2201/196 ,  H03M2201/30 ,  H03M2201/4212 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/526 ,  H03M2201/6121 ,  H03M2201/721

Abstract: A digital analog converter which is especially suitable for use in converting a digital audio signal into an analog audio signal includes a unit pulse response signal generator for successively generating unit pulse response signals at a predetermined time interval, a digital data generator for generating digital data at the predetermined time interval, a multiplier for multiplying a unit pulse response signal generated at a certain time by a predetermined item of the digital data, and a mixer for producing an analog signal output by combining the unit pulse response signals that have been multiplied by the digital data.

Abstract translation: 特别适用于将数字音频信号转换为模拟音频信号的数字模拟转换器包括用于以预定的时间间隔连续产生单位脉冲响应信号的单位脉冲响应信号发生器，用于产生数字数据的数字数据发生器 所述预定时间间隔，用于将在某一时间产生的单位脉冲响应信号乘以数字数据的预定项目的乘法器和用于产生模拟信号的混频器，所述混频器通过将已经乘以所述单位脉冲响应信号 数字数据。

公开(公告)号：US4349777A

公开(公告)日：1982-09-14

申请号：US204929

申请日：1980-11-07

Applicant: Masakazu Mitamura

Inventor： Masakazu Mitamura

IPC: G01R1/28 ,  G05F1/56 ,  H03M1/00 ,  G01R27/14 ,  G05F1/58 ,  G05F1/613

CPC classification number: G05F1/561 ,  H03M1/00 ,  H03M2201/02 ,  H03M2201/14 ,  H03M2201/3115 ,  H03M2201/3131 ,  H03M2201/3168 ,  H03M2201/4135 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4266 ,  H03M2201/60 ,  H03M2201/6121 ,  H03M2201/814

Abstract: A plurality of metal resistance elements and a metal resistance element for compensation use are formed on a common substrate and placed under the same temperature condition. A reference current is applied to the metal resistance element for compensation use to yield an auxiliary reference voltage. A plurality of switches are individually connected in series to the reference metal resistance elements and the auxiliary reference voltage is provided to the series circuits to selectively control the switches, thereby obtaining various currents.

Abstract translation: 在公共基板上形成多个金属电阻元件和用于补偿的金属电阻元件，并置于相同的温度条件下。 将参考电流施加到用于补偿使用的金属电阻元件以产生辅助参考电压。 多个开关分别与参考金属电阻元件串联连接，并且辅助参考电压被提供给串联电路以选择性地控制开关，从而获得各种电流。

公开(公告)号：US4338590A

公开(公告)日：1982-07-06

申请号：US110135

申请日：1980-01-07

Applicant: Joseph J. Connolly, Jr. ,  James B. Cecil

Inventor： Joseph J. Connolly, Jr. ,  James B. Cecil

IPC: H03M1/00 ,  H03K13/02

CPC classification number: H03M1/00 ,  H03M2201/02 ,  H03M2201/3115 ,  H03M2201/3131 ,  H03M2201/3136 ,  H03M2201/3168 ,  H03M2201/4135 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/6121 ,  H03M2201/63 ,  H03M2201/814

Abstract: A multi-stage resistive ladder network which uses extra stages to trim out resistance discrepencies. All of the stages are interconnected in a series. Nominally, current is divided in half within each stage. Half of the current is gated onto a bus in response to logic control signals, and the other half of the current is passed onto the next succeeding stage. Due to various processing limitations, the resistors comprising each stage vary slightly from their nominal value, which in turn upsets the current division. To compensate for this additional current dividing stages are serially connected to the last stage of the ladder. Current from these additional stages are selectively coupled onto the bus in response to the logic signals in addition to the current which is normally coupled thereto.

Abstract translation: 一个多级电阻梯形网络，使用额外的级来修剪阻抗差异。 所有的阶段都是相互联系的。 名义上，目前在每个阶段都分成两半。 响应于逻辑控制信号，一半的电流被门控在总线上，而另一半的电流被传递到下一个后续阶段。 由于各种处理限制，包括每个级的电阻器与它们的标称值略有不同，这反过来扰乱了当前的划分。 为了补偿这个额外的电流分级级与梯子的最后阶段串联连接。 来自这些附加级的电流除了通常耦合到其上的电流之外还响应于逻辑信号而选择性地耦合到总线上。

公开(公告)号：US3935569A

公开(公告)日：1976-01-27

申请号：US397924

申请日：1973-09-17

Applicant: Francois Marcel ,  Alain Manoury

Inventor： Francois Marcel ,  Alain Manoury

IPC: H03M1/14 ,  H03M1/00 ,  H03K13/175

CPC classification number: H03M1/00 ,  H03M2201/01 ,  H03M2201/14 ,  H03M2201/16 ,  H03M2201/196 ,  H03M2201/2208 ,  H03M2201/3115 ,  H03M2201/3131 ,  H03M2201/4105 ,  H03M2201/4135 ,  H03M2201/4204 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/52 ,  H03M2201/522 ,  H03M2201/523 ,  H03M2201/534 ,  H03M2201/60 ,  H03M2201/6121

Abstract: The invention concerns a digital coder subject to a compression law having multiple linear segments with slopes decreasing in geometrical progression having a ratio of 1/2, in which a chain of threshold detectors in a linear progression is used a first time to determine the number of the segment, then a second time to determine the position of the level on the segment.

Abstract translation: 本发明涉及经受压缩规律的数字编码器，该数字编码器具有多个线性段，其斜率以1/2的比例在几何级数上减小，其中使用线性进程中的阈值检测器链第一次来确定 该段，然后第二次确定段上的水平位置。

公开(公告)号：KR1020080007713A

公开(公告)日：2008-01-23

申请号：KR1020060066686

申请日：2006-07-18

Applicant: 고려대학교 산학협력단

Inventor： 손종필 ,  김수원

IPC: H03M1/12

CPC classification number: H03M1/0621 ,  H03M1/1265 ,  H03M2201/11 ,  H03M2201/6121 ,  H03M2201/64

Abstract: An analog to digital converter with a variable sampling period according to a noise level, and an audio recorder and a pacemaker using the same are provided to maintain an SNR(Signal to Noise Ratio) uniformly and to minimize power consumption by reducing the sampling period in the environment with low noise and increasing the sampling period in the environment with high noise. An analog to digital converter with a variable sampling period according to a noise level includes an analog to digital converting unit(110), a noise detecting unit(120), and a clock selecting unit(130). The analog to digital converting unit converts an analog input signal to a digital signal. The noise detecting unit detects the noise ingredients of the digital signal. The clock selecting unit selects one among a plurality of different clock signals according to the noise ingredients and applies the selected clock to the clock input of the analog to digital converting unit.

Abstract translation: 提供具有根据噪声电平的可变采样周期的模数转换器，以及使用该数字转换器的音频记录器和起搏器，以均匀地维持SNR（信噪比），并通过减少采样周期来最小化功耗 环境噪声低，环境噪声高的采样周期增加。 根据噪声电平具有可变采样周期的模数转换器包括模数转换单元（110），噪声检测单元（120）和时钟选择单元（130）。 模数转换单元将模拟输入信号转换为数字信号。 噪声检测单元检测数字信号的噪声成分。 时钟选择单元根据噪声成分选择多个不同时钟信号中的一个，并将所选择的时钟施加到模数转换单元的时钟输入端。

公开(公告)号：KR1020050093983A

公开(公告)日：2005-09-26

申请号：KR1020040017869

申请日：2004-03-17

Applicant: 주식회사 플레넷

Inventor： 김철 ,  우대호

IPC: H03M1/12

CPC classification number: H03M1/0658 ,  H03M1/12 ,  H03M2201/6121 ,  H03M2201/6327

Abstract: 본 발명은, 아날로그 신호를 이진 데이터로 변환하는 아날로그/디지털 변환기로서, 제공되는 아날로그 신호에서 특정 주기로 추출하여 디지털 이산 신호를 출력하는 신호 추출부와, 상기 신호 추출부로부터 출력되는 디지털 이산 신호를 n차 지연시켜 출력하는 n차 지연부와, 상기 신호 추출부로부터 출력되는 디지털 이산 신호를 n-1 번 순차적으로 지연시켜 지연되지 않은 값과 각 지연된 값에 대한 평균값을 구하여 출력하는 n차 이동 평균 필터와, 상기 n차 지연부의 출력과 상기 n차 이동 평균 필터의 출력을 비교하여 상기 디지털 이산 신호에 대응하는 이진 데이터를 출력하는 비교부를 구비한다.

公开(公告)号：KR1020100005329A

公开(公告)日：2010-01-15

申请号：KR1020080065318

申请日：2008-07-07

Applicant: 지씨티 세미컨덕터 인코포레이티드 ,  재단법인서울대학교산학협력재단

Inventor： 이희범 ,  김수환 ,  정덕균 ,  신우열

IPC: H03M1/66 ,  H03M3/02

CPC classification number: H03M1/668 ,  H03M1/70 ,  H03M2201/6121 ,  H03M2201/6309

Abstract: PURPOSE: A digital to analog converter for a continuous time sigma delta modulator is provided to improve performance of the converter by controlling a duty ratio of a clock signal. CONSTITUTION: An adding unit(110) adds up a continuous time analog input signal and an analog signal outputted from a digital to analog converter(140). A loop filter(120) includes at least one integrator to perform an integral operation. The integrator is comprised of an operational amplifier and a capacitor. A quantizer(130) performs the quantization operation based on the signal outputted from the loop filter and outputs the digital signal. The digital signal is comprised of one bit or plural bits. The digital to analog converter outputs the analog signal based on the digital signal outputted from the quantizer.

Abstract translation: 目的：提供用于连续时间Σ-Δ调制器的数模转换器，用于通过控制时钟信号的占空比来提高转换器的性能。 构成：添加单元（110）将从模拟转换器（140）输出的连续时间模拟输入信号和模拟信号相加。 环路滤波器（120）包括至少一个积分器以执行积分运算。 积分器由运算放大器和电容器组成。 量化器（130）基于从环路滤波器输出的信号进行量化操作并输出数字信号。 数字信号由一位或多位构成。 数模转换器根据从量化器输出的数字信号输出模拟信号。