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公开(公告)号：CN106027052A
公开(公告)日：2016-10-12
申请号：CN201610325878.1
申请日：2016-05-17
Applicant: 电子科技大学
IPC: H03M1/12
CPC classification number: H03M1/1245 , H03M2201/71
Abstract: 本发明属于集成电路技术领域，涉及一种电流控制延迟线电路。本发明的由多个延迟模块依次连接构成，每一个延迟模块的右移输出端接下一个延迟模块的右移输入端，每一个延迟模块的左移输出端接前一个延迟模块的左移输入端；每个延迟模块均由数据选择器、受控延迟单元、锁存器和数据分配器构成；数据选择器接左右输入信号，控制信号接外部数字控制信号；受控延迟单元接外部电流控制信号，受控延迟单元的输出端接锁存器；锁存器的输出端接数据分配器的数据输入端，数据分配器的控制信号接外部数字控制信号，数据分配器输出左右信号。本发明的有益效果为，一方面可以达到较高的采样频率；另一方面，电路结构简单，功耗和电路面积都可以达到很小。
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公开(公告)号：KR1020090054274A
公开(公告)日：2009-05-29
申请号：KR1020070121055
申请日：2007-11-26
Applicant: 연세대학교 산학협력단
IPC: H03M1/12
CPC classification number: H03M1/182 , H03M1/0617 , H03M1/1245 , H03M2201/2266 , H03M2201/71
Abstract: 아날로그 디지털 변환기가 제공된다. 본 발명의 아날로그 디지털 변환기는 복수의 기준 전압들을 생성하는 기준 전압 생성기; 상기 기준 전압들 및 입력 신호의 전압을 비교하여 제어 신호를 생성하는 히스테리시스 로직; 및 상기 제어 신호에 응답하여 디지털 출력 신호를 생성하는 계수기를 포함하고, 상기 제어 신호는 상기 디지털 출력 신호를 증가시키는 상향 명령, 상기 디지털 출력 신호를 감소시키는 하향 명령 또는 상기 디지털 출력 신호를 유지하는 유지 명령 중 어느 하나의 명령에 대응하고, 상기 기준 전압 생성기는 상기 디지털 출력 신호에 응답하여 상기 기준 전압들을 조정하는 것을 특징으로 하며, 이를 통해 ADC를 구현하는 데 요구되는 면적을 줄일 수 있고, ADC 동작 시의 소모 전력을 줄일 수 있다.
ADC, hysteresis, tracking ADC-
公开(公告)号：KR1020080006279A
公开(公告)日：2008-01-16
申请号：KR1020060065232
申请日：2006-07-12
Applicant: 삼성전자주식회사
Inventor： 김영웅
CPC classification number: H03M1/1265 , G10L25/18 , H03M1/18 , H03M2201/71
Abstract: An analog/digital conversion device using a variable sampling frequency, and a method thereof are provided to classify and sample a unique voice band to enhance a voice recognition rate. A voice signal frequency analyzer(109) analyzes a frequency component of an inputted analog signal, determines a variable sampling frequency, and provides the determined variable sampling frequency to a control unit(101). An A/D converting unit converts an analog signal into a digital signal under the instruction of the control unit(101) by using the variable sampling frequency. A D/A converting unit(117) applies the variable sampling frequency used in the A/D converting unit, and converts the digital signal into an analog signal.
Abstract translation: 提供使用可变采样频率的模拟/数字转换装置及其方法来对独特语音频带进行分类和采样以提高语音识别率。 语音信号频率分析器（109）分析输入的模拟信号的频率分量，确定可变采样频率，并将确定的可变采样频率提供给控制单元（101）。 A / D转换单元通过使用可变采样频率，在控制单元（101）的指令下将模拟信号转换为数字信号。 D / A转换单元（117）应用在A / D转换单元中使用的可变采样频率，并将数字信号转换为模拟信号。
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公开(公告)号：KR101712428B1
公开(公告)日：2017-03-06
申请号：KR1020160150033
申请日：2016-11-11
Applicant: 한화시스템 주식회사
CPC classification number: H03M1/126 , H03M1/004 , H03M1/1265 , H03M2201/71
Abstract: 표본화율을조절하기위한변조식별기및 그의표본화율조절방법이제공된다. 표본화율을조절하기위한변조식별기는, 아날로그신호들을표본화주파수로표본화하여디지털신호들로변환및 출력하는 AD 변환부와, 아날로그신호들이전송된대역폭및 심볼율중 하나를이용하여 AD 변환부에서표본화된디지털신호들의표본화간축률을결정하는간축률결정부와, AD 변환부에서출력되는디지털신호들을산출된표본화간축률을이용하여부분선택하여표본화율을하향조절하는간축률적용부와, 하향조절된표본화율에의해부분선택되는디지털신호들에대해변조식별을수행하는변조식별부를포함한다.
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公开(公告)号：KR1020160108023A
公开(公告)日：2016-09-19
申请号：KR1020150031782
申请日：2015-03-06
Applicant: 한국전자통신연구원
IPC: H03M1/12
CPC classification number: H03M1/1255 , H03M1/1285 , H03M2201/71 , H03M2201/75
Abstract: 본발명은무선통신시스템에서수신기의아날로그-디지털변환기(analog-digital converter, ADC)의제어장치및 방법에관한것으로, PN 코드생성기및 코드판별부로부터동기정보를입력받아동기화정도에따른 ADC의샘플링주파수를제어하는것이다. 본발명에따르면, 수신기의프레임동기화정도의상태정보를바탕으로샘플링시간을점차세밀하게제어하여정확한샘플링정보취득과정밀한프레임동기가가능하여고정밀 ranging에필요한동기화성능을개선할 수있다.
Abstract translation: 本发明涉及用于控制无线通信系统中的接收机的模数转换器（ADC）的装置和方法。 通过从代码确定部分和PN代码发生器接收同步信息来控制根据同步电平的ADC的采样频率。 根据本发明，基于接收机的帧同步电平的状态信息逐渐精确地控制采样时间。 因此，可以进行准确的采样信息采集和精确的帧同步。 可以提高高精度测距所需的同步性能。
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Patent Agency Ranking6.发明公开다채널 생체 신호 검출을 위한 연속 근사 레지스터 아날로그-디지털 변환기 및 이를 이용한 아날로그 디지털 변환 방법 有权用于提取多通道BI0信号和模拟数字转换方法的连续逼近寄存器模拟转换器
公开(公告)号：KR1020140087375A
公开(公告)日：2014-07-09
申请号：KR1020120157543
申请日：2012-12-28
Applicant: 중앙대학교 산학협력단
IPC: H03M1/38
CPC classification number: H03M1/38 , H03M1/122 , H03M1/1245 , H03M2201/192 , H03M2201/2233 , H03M2201/71
Abstract: A successive approximation register analog-to-digital converter and an analog-to-digital converting method using the same are disclosed. According to the present invention, the successive approximation register analog-to-digital converter comprises: a first split capacitor array for converting digital signals inputted in sequence into analog signals and generating a reference voltage signal; a second split capacitor array for selectively holding one among a plurality of analog input voltages inputted from the outside and generating a hold voltage signal; a comparison unit for comparing the reference voltage signal with the hold voltage signal and outputting a comparison signal; and a signal processing unit for sequentially outputting the digital signals to the first split capacitor array by using the comparison signal and outputting a channel control signal to the second split capacitor array, wherein the second split capacitor array generates the hold voltage signal with respect to one among the plurality of analog input voltages according to the channel control signal.
Abstract translation: 公开了逐次逼近寄存器模数转换器和使用其的模数转换方法。 根据本发明，逐次逼近寄存器模数转换器包括：第一分离电容器阵列，用于将依次输入的数字信号转换为模拟信号并产生参考电压信号; 第二分割电容器阵列，用于选择性地保持从外部输入的多个模拟输入电压中的一个，并产生保持电压信号; 比较单元，用于将参考电压信号与保持电压信号进行比较并输出比较信号; 以及信号处理单元，用于通过使用比较信号将数字信号顺序地输出到第一分离电容器阵列，并将通道控制信号输出到第二分离电容器阵列，其中第二分离电容器阵列相对于一个产生保持电压信号 在根据信道控制信号的多个模拟输入电压中。
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公开(公告)号：KR1020080047192A
公开(公告)日：2008-05-28
申请号：KR1020060117226
申请日：2006-11-24
Applicant: 한국과학기술원
IPC: H03M1/12
CPC classification number: H03M1/1245 , H03M1/20 , H03M2201/625 , H03M2201/71
Abstract: A method for converting analog to digital with enhanced resolution by oversampling is provided to improve resolution by using a voltage controlled oscillator to quantize an analog signal and determining a digital code to be outputted by giving weighted values to various analog values after sampling the various analog values for one cycle of a reference clock. A method for converting analog to digital with enhance resolution by oversampling includes the steps of: generating an oversampling clock having a frequency N times more than a reference clock(S200); converting M analog input signals into M digital values(S400) after sampling and quantizing the M analog input signals for each cycle of the reference clock by being synchronized with the oversampling clock(S300); determining a weighted value for each of the M digital values(S600); and determining one digital code on the basis of the M digital values and the weighted value(S700).
Abstract translation: 提供了通过过采样将模拟转换为数字增强分辨率的方法，通过使用压控振荡器来量化模拟信号并通过在对各种模拟值进行采样之后给予各种模拟值的加权值来确定要输出的数字码来确定要输出的数字码，以提高分辨率 用于参考时钟的一个周期。 一种通过过采样将模拟转换为数字增强分辨率的方法包括以下步骤：产生具有比参考时钟N倍的频率的过采样时钟（S200）; 通过与过采样时钟同步（S300）对参考时钟的每个周期对M个模拟输入信号进行采样和量化后，将M个模拟输入信号转换为M个数字值（S400）。 确定每个M个数字值的加权值（S600）; 并根据M个数字值和加权值确定一个数字代码（S700）。
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公开(公告)号：KR1020090072053A
公开(公告)日：2009-07-02
申请号：KR1020070140028
申请日：2007-12-28
Applicant: 연세대학교 산학협력단
IPC: H03M3/02
CPC classification number: H03M3/392 , H03M3/32 , H03M2201/62 , H03M2201/71
Abstract: A time-interleaved sigma-delta modulator using a single amplifier architecture is provided to implement the modulator with a high dynamic range by increasing an effective sampling frequency. A combiner(210) amplifies and adds a signal inputted from the outside, a fed back signal after quantization, and the fed back signal without the quantization. One or more integrating units delays the signal outputted from the combiner as much as the predetermined clock and multiplies the delayed signal by a constant coefficient. The integrating unit adds the inputted value to the signal and provides the added signal as the fed back signal without quantization to the combiner. A quantizer(220) quantizes the signal outputted from the combiner. A clock delay unit(225) delays the signal outputted from the quantizer and provides the delayed signal as the fed back signal after quantization.
Abstract translation: 提供了使用单放大器架构的时间交错式Σ-Δ调制器，以通过增加有效采样频率来实现具有高动态范围的调制器。 组合器（210）将从外部输入的信号，量化后的反馈信号和反馈信号放大并相加而不进行量化。 一个或多个积分单元将从组合器输出的信号延迟到预定时钟，并将延迟的信号乘以恒定系数。 积分单元将输入的值添加到信号中，并将相加的信号作为反馈信号提供给组合器而不进行量化。 量化器（220）量化从组合器输出的信号。 时钟延迟单元（225）延迟从量化器输出的信号，并且在量化之后提供延迟的信号作为反馈信号。
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公开(公告)号：KR1020080051408A
公开(公告)日：2008-06-11
申请号：KR1020060122430
申请日：2006-12-05
Applicant: 한국과학기술원
IPC: H04N5/208
CPC classification number: H03M1/1285 , H03K19/20 , H03M2201/71 , H04N7/0117
Abstract: An analog-digital converter capable of adjusting resolution and a conversion method therefor are provided to be operated in a broadband sampling frequency by using a VCO(Voltage Controlled Oscillator) and adjust the resolution and power consumption without a structural change. An input adjusting circuit(100) changes a level of an input signal according to a selected resolution mode. A digital code generating circuit(200) generates a digital code for the converted input signal. The input adjusting circuit includes a sample-end-hold circuit for sampling and holding an analog input signal in response to a sampling clock.
Abstract translation: 通过使用VCO（压控振荡器），能够调整分辨率的模拟数字转换器及其转换方法以宽带采样频率工作，并且在没有结构变化的情况下调整分辨率和功耗。 输入调整电路（100）根据选择的分辨率模式改变输入信号的电平。 数字码产生电路（200）产生用于转换的输入信号的数字码。 输入调整电路包括采样保持电路，用于响应采样时钟采样和保持模拟输入信号。
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公开(公告)号：KR1020080008481A
公开(公告)日：2008-01-24
申请号：KR1020060067789
申请日：2006-07-20
Applicant: 한양대학교 산학협력단
Inventor： 권오경
CPC classification number: G09G3/2092 , G09G3/3275 , G09G3/3688 , G09G2310/0294 , G11C27/02 , H03M1/66 , H03M2201/71
Abstract: A data driver and a driving method thereof are provided to minimize a mounting area of circuits of D/A converters by constituting the circuits in the same structure. A digital/analog converter includes a current input stage, a first sampling/hold circuit(110), a second sampling/hold circuit(120) and a diode connection circuit(130). The first sampling/hold circuit samples a half value of an input current applied through the current input stage and a half value of the current held by the diode connection circuit. The second sampling/hold circuit samples the current held by the first sampling/hold circuit. Each of the first and second sampling/hold circuits has at least one unit sampling/hold circuit consisting of one capacitor, one transistor and one switch.
Abstract translation: 提供数据驱动器及其驱动方法，通过构成相同结构的电路来最小化D / A转换器的电路的安装面积。 数字/模拟转换器包括电流输入级，第一采样/保持电路（110），第二采样/保持电路（120）和二极管连接电路（130）。 第一采样/保持电路采样通过电流输入级施加的输入电流的半值和由二极管连接电路保持的电流的一半值。 第二采样/保持电路对由第一采样/保持电路保持的电流进行采样。 第一和第二采样/保持电路中的每一个具有由一个电容器，一个晶体管和一个开关组成的至少一个单元采样/保持电路。
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