公开(公告)号：US20250029653A1

公开(公告)日：2025-01-23

申请号：US18714879

申请日：2022-05-12

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Zhengyong ZHU ,  Bokmoon KANG ,  Dan WANG ,  Chao ZHAO

IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/4091 ,  G11C11/4094

Abstract: Provided is a memory. The memory includes at least one memory array and at least one control circuit, wherein the memory array comprises a plurality of memory cells arranged in an array as well as read wordlines and read bitlines for read operations, wherein each of the memory cells comprises a first transistor and a second transistor. The control circuit is configured to transmit, during a pre-processing stage, a first voltage to the read wordline and the read bitline; transmit, during a pre-charging stage, a second voltage to the read bitline; and transmit, during a read-sensing stage, a third voltage to the read wordline.

公开(公告)号：US12183807B2

公开(公告)日：2024-12-31

申请号：US17783624

申请日：2021-12-23

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY ,  INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Weixing Huang ,  Huilong Zhu

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78

Abstract: A semiconductor device and a method for manufacturing the same. A first electrode layer, a semiconductor layer, and a second electrode layer are formed on a substrate. The semiconductor layer is etched form a sidewall to form a cavity. A channel layer is formed at the cavity and sidewalls of the first electrode layer and the second electrode layer. The channel layer includes a first channel part located in the cavity and a second channel part located outside the cavity. The first channel part is filled with a dummy gate layer. The dummy gate layer is etched from a sidewall. The second channel part and the first channel part, which is in contact with upper and lower surfaces of the dummy gate layer are removed to form a recess. The recess is filled with a dielectric material to form an isolation sidewall.

公开(公告)号：US20240389306A1

公开(公告)日：2024-11-21

申请号：US18691823

申请日：2022-09-23

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Xiangsheng Wang ,  Guilei Wang ,  Chao Zhao

IPC: H10B12/00

Abstract: The semiconductor device includes: a substrate; a plurality of memory cell columns, wherein each memory cell column includes a plurality of memory cells, arranged and stacked on one side of the substrate in a first direction, and the plurality of memory cell columns are arranged on the substrate in a second direction and in a third direction to form an array; the memory cells each include a transistor and a capacitor, the transistor including a semiconductor layer and a gate, and semiconductor layer includes a source region, an inversion channel region and a drain region; a plurality of bit lines, extending in the first direction, wherein the source regions of the transistors of the plurality of memory cells in two adjacent memory cell columns in the second direction, are all connected to one bit line; and a plurality of word lines, extending in the third direction.

公开(公告)号：US20240313103A1

公开(公告)日：2024-09-19

申请号：US18263472

申请日：2021-12-14

Applicant: Beijing Superstring Academy of Memory Technology ,  Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Huilong Zhu ,  Zhongrui Xiao

IPC: H01L29/78 ,  H01L21/027 ,  H01L21/306 ,  H01L29/10 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7802 ,  H01L21/0274 ,  H01L21/30625 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/66712

Abstract: The vertical MOSFET device includes: an active region including a first source/drain layer, a channel layer and a second source/drain layer vertically stacked on a substrate in sequence, wherein an outer periphery of the channel layer is recessed with respect to outer peripheries of the first source/drain layer and the second source/drain layer; a spacing layer including an upper spacing layer and a lower spacing layer, wherein the upper spacing layer and the lower spacing layer are both in contact with a side surface of the channel layer and are not in communication with each other; and a gate stack formed at least on a lateral outer periphery of the channel layer and embedded in a groove space between the upper spacing layer and the lower spacing layer.

公开(公告)号：US20240145591A1

公开(公告)日：2024-05-02

申请号：US17770871

申请日：2021-12-13

Applicant: Beijing Superstring Academy of Memory Technology ,  INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Zhuo CHEN ,  Huilong ZHU

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7827 ,  H01L29/1037 ,  H01L29/41741 ,  H01L29/41775 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66666

Abstract: The present disclosure relates to a vertical MOSFET device, a manufacturing method and application thereof. The method includes: forming a first silicon layer, a first germanium-silicon layer, a second germanium-silicon layer, a third germanium-silicon layer and a second silicon layer that are vertically stacked from bottom to top on a substrate, where molar contents of germanium in the first germanium-silicon layer and the third germanium-silicon layer are both greater than the content of germanium in the second germanium-silicon layer; etching to form a nano stack structure; selectively etching the first germanium-silicon layer and the third germanium-silicon layer to form a first groove and a third groove; forming inner spacers of an extension region in the first groove and the third groove; selectively etching the second germanium-silicon layer to form a gate groove; forming a dummy gate in the gate groove; forming sources/drains; forming an active region with a shallow trench isolation layer; and removing the dummy gate to form a gate dielectric layer and a gate. The present disclosure can well control the size of channel, the size of inner spacers of the extension region, the size of the gates, and the like, and is applicable to either nanosheet or nanowire structures.

公开(公告)号：US20240114672A1

公开(公告)日：2024-04-04

申请号：US18256669

申请日：2021-12-14

Applicant: Beijing Superstring Academy of Memory Technology ,  INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Ziyi Liu ,  Huilong Zhu

IPC: H10B10/00

CPC classification number: H10B10/125

Abstract: A memory device includes a memory unit array on substrate, the memory unit array includes a plurality of memory units, each memory unit includes: a left and a right stack arranged at intervals in a horizontal direction. The left stack and right stacks each include a lower isolation layer, PMOS layer, first NMOS layer, upper isolation layer and second NMOS layer stacked on the substrate sequentially. The PMOS layer, and the first and second NMOS layer each include first source/drain layer, channel layer and second source/drain layer vertically stacked. The channel layer is laterally recessed relative to the first and second source/drain layers; and a gate stack between the first and second source/drain layers in the vertical direction, and disposed on opposite sides of the channel layer and embedded into a lateral recess of the channel layer.

公开(公告)号：US11948616B2

公开(公告)日：2024-04-02

申请号：US17808404

申请日：2022-06-23

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC. ,  BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Xiaoguang Wang ,  Dinggui Zeng ,  Huihui Li ,  Jiefang Deng ,  Kanyu Cao

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

CPC classification number: G11C11/161 ,  G11C11/1655 ,  H10B61/22 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a transistor, including a control terminal, a first terminal, and a second terminal; a first magnetic memory structure, a bottom electrode of which is electrically connected to the first terminal of the transistor; a second magnetic memory structure, a top electrode of which is electrically connected to the first terminal of the transistor, the bottom electrode of the first magnetic memory structure is located in a same layer with a bottom electrode of the second magnetic memory structure; a first bit line, electrically connected to a top electrode of the first magnetic memory structure; a second bit line, electrically connected to the bottom electrode of the second magnetic memory structure; and a selection line, electrically connected to a second terminal of the transistor.

公开(公告)号：US20240061596A1

公开(公告)日：2024-02-22

申请号：US18312968

申请日：2023-05-05

Applicant: BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Jin DAI ,  Yunsen ZHANG

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0604 ,  G06F3/0679

Abstract: Provided are a computational storage system, computational storage processor, solid-state drive (SSD) and data storing method. The method may include receiving a first storing instruction based on a storage object, generating a second storing instruction based on a flash memory address according to information carried by the first storing instruction and SSD resource information maintained locally, and sending the generated second storing instruction to the SSD. The SSD resource information may include resource occupation information in the SSD. Generating the second storing instruction may include parsing an identification of a storage object, data length information and a starting source address of entire data, allocating a flash memory address or addresses in one or more SSDs for storing data of the storage object according to the data length information and the resource occupancy information in the SSD, and generating the second storing instructions for each SSD.

公开(公告)号：US20230422467A1

公开(公告)日：2023-12-28

申请号：US17934647

申请日：2022-09-23

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC. ,  BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Deyuan XIAO ,  Yong Yu ,  Guangsu Shao

IPC: H01L27/108

CPC classification number: H01L27/10873 ,  H01L27/10814

Abstract: The present disclosure is applicable to the field of semiconductors, and provides a transistor, a fabrication method, and a memory. The transistor includes: a semiconductor substrate, silicon support pillars, located on the semiconductor substrate, and gates, each of the gates arranged around one of the silicon support pillars. A side surface of each of the gates close to the silicon support pillar is a first surface, a side surface of each of the gates distant from the silicon support pillar is a second surface, and the length of the first surface is less than the length of the second surface. The length of the first surface of each of the gates is less than the length of the channel region of each of the silicon support pillars.

公开(公告)号：US20230301070A1

公开(公告)日：2023-09-21

申请号：US17872117

申请日：2022-07-25

Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC. ,  BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

Inventor： Deyuan Xiao ,  Yong Yu ,  Guangsu Shao

IPC: H01L27/108

CPC classification number: H01L27/10841 ,  H01L27/10864

Abstract: Provided are a semiconductor structure and a method for manufacturing the same, a memory device and a method for manufacturing the same. The semiconductor structure includes at least one transistor. Each of the at least one transistor includes a channel including a first semiconductor layer and a second semiconductor layer disposed around the first semiconductor layer. The second semiconductor layer introduces strain into the channel.