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    Probe card for testing semiconductor device, and semiconductor device test method
    92.
    发明公开
    Probe card for testing semiconductor device, and semiconductor device test method 审中-公开
    Halbleiter-Sondenkartenprüfvorrichtungund Halbleitervorrichtungs-Prüfverfahren

    公开(公告)号：EP2023386A2

    公开(公告)日：2009-02-11

    申请号：EP08167742.9

    申请日：2000-04-14

    Applicant: Fujitsu Microelectronics Limited

    Inventor： Maruyama, Shigeyuki

    IPC: H01L21/66 ,  H01L23/48

    CPC classification number: G01R1/0408 ,  G01R1/07314 ,  G01R31/2831

    Abstract: A probe card for testing a plurality of semiconductor devices on a wafer comprising: a flexible contact board; a plurality of contact electrodes provided on the contact board; at least one rigid base provided on at least one side of the contact board, said at least one rigid base having apertures corresponding to positions of the contact electrodes; and wiring connecting the contact electrodes to respective external connecting terminals; wherein the rigid base is formed by a single layer or multiple layers, having a first electrode connected to the wiring on a lower surface of the rigid base and a second electrode connected to the first electrode on an upper surface of the rigid base.

    Abstract translation: 一种用于测试晶片上的多个半导体器件的探针卡，包括：柔性接触板; 设置在所述接触板上的多个接触电极; 设置在所述接触板的至少一侧上的至少一个刚性基座，所述至少一个刚性基部具有对应于所述接触电极的位置的孔; 以及将接触电极连接到各个外部连接端子的布线; 其中所述刚性基底由单层或多层形成，所述单层或多层具有连接到所述刚性基底的下表面上的布线的第一电极和在所述刚性基底的上表面上连接到所述第一电极的第二电极。

    Successive approximation analog-to-digital converter
    94.
    发明公开
    Successive approximation analog-to-digital converter 失效
    Analog-Digitalwandler mit schrittweiserAnnäherung

    公开(公告)号：EP0729236A1

    公开(公告)日：1996-08-28

    申请号：EP96301129.1

    申请日：1996-02-20

    Applicant: FUJITSU MICROELECTRONICS LIMITED

    Inventor： Dedic, Ian Juso ,  Beckett, Andrew David

    IPC: H03M1/46

    CPC classification number: H03M1/0697 ,  H03M1/0695 ,  H03M1/46

    Abstract: An analog-to-digital converter (ADC) operates repetitively to perform a series of conversion cycles. A comparator (9) receives an analog input signal (V IN ) and compares it with an analog comparison signal produced by a digital-to-analog converter (5). A successive-approximation register circuit (22) holds a digital trial signal value and uses it to control the value of the analog comparison signal in each conversion cycle so as to perform up to two comparisons per cycle, thereby to produce digital data that has a first value ("+1") when the input signal value is greater than a first comparison value (V C 1 ) and that has a second value ("-1") when the input signal value is less than a second comparison value (V C2 ) and that in all other cases has a third value ("0"). The first comparison value (V C 1 ) is set higher than the trial signal value determined for use in the cycle concerned, and the second comparison value is set lower than that trial signal value. Each comparison value differs from the trial signal value by the same predetermined amount. The successive-approximation register circuit (22) adjusts the said trial signal value in each cycle in dependence upon the said digital data produced in the cycle concerned so as to tend to bring that value into closer correspondence with the input signal value.
    Such an ADC can employ the same analog circuits (5,7,9) as a conventional successive-approximation ADC but can operate at higher speeds because errors in the decisions made in one conversion cycle are, within reasonable limits, corrected automatically in subsequent conversion cycles.

    Abstract translation: 模数转换器（ADC）重复操作以执行一系列转换周期。 比较器（9）接收模拟输入信号（VIN）并将其与由数模转换器（5）产生的模拟比较信号进行比较。 逐次逼近寄存器电路（22）保持数字试用信号值，并使用它来控制每个转换周期中的模拟比较信号的值，以便每个周期执行两次比较，从而产生数字数据，其具有 当输入信号值大于第一比较值（VC1）并且当输入信号值小于第二比较值（VC2）时具有第二值（“-1”）时的第一值（“+1”）， 而在所有其他情况下，都有第三个值（“0”）。 将第一比较值（VC1）设定为高于在所述循环中使用的试验信号值，并将第二比较值设定为低于该试验信号值。 每个比较值与试验信号值相差相同的预定量。 逐次逼近寄存器电路（22）根据相关周期中产生的所述数字数据来调整每个周期中的所述试验信号值，以便使该值与输入信号值更接近。 这样的ADC可以采用与传统的逐次逼近ADC相同的模拟电路（5,7,9），但是可以以更高的速度工作，因为在一个转换周期中做出的决策中的错误在合理的限度内在随后的转换中自动校正 周期。

    Semiconductor device
    95.
    发明授权
    Semiconductor device 有权
    Halbleitervorrichtung

    公开(公告)号：EP2175487B1

    公开(公告)日：2015-03-11

    申请号：EP10000804.4

    申请日：2003-07-24

    Applicant: Fujitsu Microelectronics Limited

    Inventor： Watanabe, Kenichi

    IPC: H01L23/522 ,  H01L23/532 ,  H01L23/528

    CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective filling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

    Abstract translation: 半导体器件包括：形成在衬底10上的绝缘膜40,42; 掩埋在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及埋入孔形通孔60和槽状通路孔66a中的埋入导体70,72a，其中，形成沟槽状通路孔66a的宽度小于孔的宽度 由此防止了埋入导体的缺陷填充，可以防止层间绝缘膜的破裂。 可以减少导体塞上的步骤，使得该步骤不会影响上互连层和绝缘层。 因此，可以防止与上部互连层的不良接触以及在形成膜时发生的问题，从而可以使半导体器件具有高的耐水性和高的互连可靠性。

    Semiconductor device and method for fabricating the same
    97.
    发明公开
    Semiconductor device and method for fabricating the same 有权
    Halbleitervorrichtung und Herstellungsverfahren

    公开(公告)号：EP2175487A3

    公开(公告)日：2012-04-18

    申请号：EP10000804.4

    申请日：2003-07-24

    Applicant: Fujitsu Microelectronics Limited

    Inventor： Watanabe, Kenichi

    IPC: H01L23/522 ,  H01L23/532

    CPC classification number: H01L21/76877 ,  H01L21/76804 ,  H01L21/76843 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53204 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/562 ,  H01L23/58 ,  H01L23/585 ,  H01L29/0607 ,  H01L29/0611 ,  H01L29/0619 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The semiconductor device comprises: insulating films 40, 42 formed over a substrate 10; an interconnection 58 buried in at least a surface side of the insulating films 40, 42; insulating films 60, 62 formed on the insulating film 42 and including a hole-shaped via-hole 60 and a groove-shaped via-hole 66a having a pattern bent at a right angle; and buried conductors 70, 72a buried in the hole-shaped via-hole 60 and the groove-shaped via-hole 66a, wherein the groove-shaped via-hole 66a is formed to have a width which is smaller than a width of the hole-shaped via-hole 66. Whereby, the defective filling of the buried conductor is prevented, and the cracking of the inter-layer insulating film can be prevented. Steps on the conductor plug can be reduced, so that the step cannot be influential on the upper interconnection layers and insulating layers. Accordingly, defective contact with the upper interconnection layer and the problems taking place in forming films can be prevented, and resultantly the semiconductor device can have high water resistance and high interconnection reliability.

    Abstract translation: 半导体器件包括：形成在衬底10上的绝缘膜40,42; 掩埋在绝缘膜40,42的至少表面侧的互连件58; 绝缘膜60,62形成在绝缘膜42上并且包括孔形通孔60和具有以直角弯曲的图案的槽形通孔66a; 以及埋入孔形通孔60和槽状通路孔66a中的埋入导体70,72a，其中，形成沟槽状通路孔66a的宽度小于孔的宽度 由此防止了埋入导体的缺陷填充，可以防止层间绝缘膜的破裂。 可以减少导体塞上的步骤，使得该步骤不会影响上互连层和绝缘层。 因此，可以防止与上部互连层的不良接触以及在形成膜时发生的问题，从而可以使半导体器件具有高的耐水性和高的互连可靠性。

    Scheduling in a multicore architecture
    99.
    发明公开
    Scheduling in a multicore architecture 审中-公开
    在多核架构中进行调度

    公开(公告)号：EP2328076A1

    公开(公告)日：2011-06-01

    申请号：EP10192097.3

    申请日：2006-09-27

    Applicant: Coware, Inc. ,  Fujitsu Microelectronics Limited

    Inventor： Lipett, Mark David

    IPC: G06F9/40

    CPC classification number: G06F15/80 ,  G06F1/3203 ,  G06F9/466 ,  G06F9/4893 ,  G06F9/5027 ,  G06F9/5038 ,  G06F2209/483 ,  G06F2209/5011 ,  Y02D10/24

    Abstract: This invention relates to scheduling threads in a multicore processor. Executable transactions may scheduled using at least one distribution queue, which lists executable transactions in order of eligibility for execution, and multilevel scheduler which comprises a plurality of linked individual executable transaction schedulers. Each of these includes a scheduling algorithm for determining the most eligible executable transaction for execution. The most eligible executable transaction is outputted from the multilevel scheduler to the at least one distribution queue.

    Abstract translation: 本发明涉及在多核处理器中调度线程。 可执行事务可以使用至少一个分配队列和包括多个链接的单独可执行事务调度器的多级调度器来调度，所述至少一个分配队列以可执行资格的顺序列出可执行事务。 其中每一个都包括一个调度算法，用于确定执行最合适的可执行事务。 最合格的可执行事务从多级调度器输出到至少一个分发队列。

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