公开(公告)号：US20170263560A1

公开(公告)日：2017-09-14

申请号：US15419091

申请日：2017-01-30

Applicant: J-Devices Corporation

Inventor： Hiroaki MATSUBARA ,  Tomoshige CHIKAI ,  Naoki HAYASHI ,  Toshihiro IWASAKI

IPC: H01L23/538 ,  H01L21/768

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/2518 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244

Abstract: An object of the present invention is to provide an interconnect structure in which the current capacity of an interconnect pattern involving a large amount of current is increased without preventing miniaturization of signal lines and increasing film thickness. To accomplish this object, the present invention is configured as an interconnect structure including a resin layer; and interconnects formed on the resin layer, wherein the resin layer has a plurality of parallel grooves in an area in which the interconnects are formed, and the interconnects are formed of a plating film created on a resin layer front surface in the area, in which the interconnects are formed, and on inner wall surfaces of the plurality of grooves.

公开(公告)号：US20170256453A1

公开(公告)日：2017-09-07

申请号：US15409631

申请日：2017-01-19

Applicant: J-DEVICES CORPORATION

Inventor： Takahiro YADA ,  Katsushi YOSHIMITSU

IPC: H01L21/78 ,  H01L21/306 ,  H01L21/56 ,  H01L21/304 ,  H01L25/065 ,  H01L23/31

Abstract: A manufacturing method of a semiconductor package which improves productivity and can manufacture high-quality semiconductor packages is provided. The manufacturing method of a semiconductor package includes arranging a plurality of semiconductor devices at intervals on a first surface side of a support substrate, forming a first insulating resin layer forming wiring connected to each of the plurality of semiconductor devices and embeds the plurality of semiconductor devices, cutting from the first surface side in areas between the plurality of semiconductor devices, forming a first groove portion penetrating the first insulating resin layer and exposing the support substrate, and dividing individual semiconductor packages by forming a resist pattern having openings arranged corresponding to the first groove portion on a second surface on the opposite side of the first surface, etching the openings from the second surface side, and forming a second groove portion on the second surface side

公开(公告)号：US09721900B2

公开(公告)日：2017-08-01

申请号：US15364851

申请日：2016-11-30

Applicant: J-Devices Corporation

Inventor： Naoki Hayashi

IPC: H01L23/28 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L21/768 ,  H01L21/683

CPC classification number: H01L23/5389 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/05147 ,  H01L2224/06181 ,  H01L2224/215 ,  H01L2924/01029

Abstract: Provided is a bonding method to construct a bonding with high thermal reliability between electrodes formed on both chip surfaces of a semiconductor device and wiring. The bonding method includes: bonding a semiconductor chip over a first substrate with a bonding film interposed therebetween; forming a first insulating film over the semiconductor chip; forming a first via in the first insulating film; forming a first wiring over the first insulating film so as to be electrically connected to the semiconductor chip through the first via; forming a second via in the bonding film; and forming a second wiring under the semiconductor chip so as to be electrically connected to the semiconductor chip through the second via.

公开(公告)号：US09685376B2

公开(公告)日：2017-06-20

申请号：US14801437

申请日：2015-07-16

Applicant: J-DEVICES CORPORATION

Inventor： Yoshihiko Ikemoto ,  Hiroshi Inoue ,  Kiminori Ishido ,  Hiroaki Matsubara ,  Yukari Imaizumi

IPC: H01L23/24 ,  H01L21/44 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/19 ,  H01L25/0657 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2224/83

Abstract: A semiconductor device including: a support plate 1; a semiconductor chip 2 mounted on one principal surface of the support plate 1 via an adhesive layer, with the element circuit surface of the chip being directed upward; an insulation material layer 4 that seals the semiconductor chip 2 and the periphery of the semiconductor chip; openings formed on an electrode arranged on the element circuit surface of the semiconductor chip 2 in the insulation material layer 4; conductive portions 6 formed in the openings so as to be connected to the electrode of the semiconductor chip; a wiring layer 5 formed on the insulation material layer 4 so as to be connected to the conductive portions 6 and partially extending to the peripheral region of the semiconductor chip 2; and external electrodes 7 formed on the wiring layer 5.

公开(公告)号：US20170170123A1

公开(公告)日：2017-06-15

申请号：US15364851

申请日：2016-11-30

Applicant: J-Devices Corporation

Inventor： Naoki HAYASHI

IPC: H01L23/538 ,  H01L21/768 ,  H01L21/683 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/6835 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68318 ,  H01L2221/68359 ,  H01L2221/68363 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2221/68386 ,  H01L2224/05147 ,  H01L2224/06181 ,  H01L2224/215 ,  H01L2924/01029

Abstract: Provided is a bonding method to construct a bonding with high thermal reliability between electrodes formed on both chip surfaces of a semiconductor device and wiring. The bonding method includes: bonding a semiconductor chip over a first substrate with a bonding film interposed therebetween; forming a first insulating film over the semiconductor chip; forming a first via in the first insulating film; forming a first wiring over the first insulating film so as to be electrically connected to the semiconductor chip through the first via; forming a second via in the bonding film; and forming a second wiring under the semiconductor chip so as to be electrically connected to the semiconductor chip through the second via.

公开(公告)号：US20170110432A1

公开(公告)日：2017-04-20

申请号：US15290557

申请日：2016-10-11

Applicant: J-DEVICES CORPORATION

Inventor： Minoru KAI

IPC: H01L23/00 ,  H01L21/67 ,  H01L21/68

CPC classification number: H01L24/75 ,  H01L21/67132 ,  H01L21/67144 ,  H01L21/681 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/75312 ,  H01L2224/75316 ,  H01L2224/7532 ,  H01L2224/75702 ,  H01L2224/75745 ,  H01L2224/75753 ,  H01L2224/75822 ,  H01L2224/75824 ,  H01L2224/8313 ,  H01L2224/83132 ,  H01L2224/8317 ,  H01L2224/8318 ,  H01L2224/83191 ,  H01L2924/00014 ,  H01L2924/0715 ,  H01L2924/0635 ,  H01L2924/06 ,  H01L2924/013 ,  H01L2924/00012

Abstract: A press fitting head comprising an elastic member in a part where the press fitting head contacts a semiconductor device, and an alignment mark recognition area capable of detecting an optically readable marker provided on a surface to be contacted to the semiconductor device is provided. Additionally, a semiconductor manufacturing apparatus in which the press fitting head is applied is provided.

公开(公告)号：US20160218086A1

公开(公告)日：2016-07-28

申请号：US14994963

申请日：2016-01-13

Applicant: J-DEVICES CORPORATION

Inventor： Makoto MODA

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L25/0657 ,  H01L23/36 ,  H01L23/49861 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L29/0657 ,  H01L2224/05554 ,  H01L2224/26145 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29339 ,  H01L2224/2939 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49173 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83365 ,  H01L2225/06555 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/10158 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A semiconductor device is provided including a package substrate, and a plurality of semiconductor chips stacked above the package substrate, at least one of the plurality of semiconductor chips including a step part in a periphery edge part of a rear surface,

Abstract translation: 提供了一种半导体器件，包括封装衬底和堆叠在封装衬底之上的多个半导体芯片，所述多个半导体芯片中的至少一个包括在后表面的周边边缘部分中的台阶部分，

公开(公告)号：US20160172265A1

公开(公告)日：2016-06-16

申请号：US14944480

申请日：2015-11-18

Applicant: J-DEVICES CORPORATION

Inventor： Kiyoaki HASHIMOTO

IPC: H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L25/0652 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5389 ,  H01L23/562 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/82 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2224/83

Abstract: A semiconductor package includes a first semiconductor device provided on a support substrate; a first encapsulation material covering the first semiconductor device; a first line provided on the first encapsulation material, the first line being connected with the first semiconductor device; an intermediate buffer layer covering the first line, and a second encapsulation material provided on the intermediate buffer layer. The first encapsulation material and the second encapsulation material are each formed of an insulating material different from an insulating material used to form the intermediate buffer layer. A second semiconductor device covered with the second encapsulation material may be provided on the intermediate buffer layer.

Abstract translation: 半导体封装包括设置在支撑基板上的第一半导体器件; 覆盖所述第一半导体器件的第一封装材料; 设置在所述第一封装材料上的第一线，所述第一线与所述第一半导体器件连接; 覆盖第一线的中间缓冲层和设置在中间缓冲层上的第二封装材料。 第一封装材料和第二封装材料均由与用于形成中间缓冲层的绝缘材料不同的绝缘材料形成。 覆盖有第二封装材料的第二半导体器件可以设置在中间缓冲层上。

公开(公告)号：US20160027715A1

公开(公告)日：2016-01-28

申请号：US14803889

申请日：2015-07-20

Applicant: J-DEVICES CORPORATION

Inventor： Shinji WATANABE ,  Sumikazu HOSOYAMADA ,  Shingo NAKAMURA ,  Hiroshi DEMACHI ,  Takeshi MIYAKOSHI ,  Tomoshige CHIKAI ,  Kiminori ISHIDO ,  Hiroaki MATSUBARA ,  Takashi NAKAMURA ,  Hirokazu HONDA ,  Yoshikazu KUMAGAYA ,  Shotaro SAKUMOTO ,  Toshihiro IWASAKI ,  Michiaki TAMAKAWA

IPC: H01L23/373 ,  H05K1/18 ,  H01L23/31 ,  H05K1/02 ,  H01L25/065 ,  H01L23/367

CPC classification number: H05K1/181 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3733 ,  H01L23/4334 ,  H01L23/49816 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15331 ,  H01L2924/1815 ,  H05K1/0204 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/141 ,  H05K2201/0275 ,  H05K2201/066 ,  H05K2201/10515 ,  H05K2203/1311 ,  H05K2203/1322 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.

Abstract translation: 叠层半导体封装包括：第一半导体封装，包括第一电路板和安装在第一电路板上的第一半导体器件; 第二半导体封装，包括第二电路板和安装在第二电路板上的第二半导体器件，第二半导体封装堆叠在第一半导体封装上; 以及设置在第一半导体器件上的传热部件和第一电路板的一部分，该部分围绕第一半导体器件。

公开(公告)号：US20160027695A1

公开(公告)日：2016-01-28

申请号：US14801437

申请日：2015-07-16

Applicant: J-DEVICES CORPORATION

Inventor： Yoshihiko IKEMOTO ,  Hiroshi INOUE ,  Kiminori ISHIDO ,  Hiroaki MATSUBARA ,  Yukari IMAIZUMI

IPC: H01L21/78 ,  H01L23/48

CPC classification number: H01L21/78 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/19 ,  H01L25/0657 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2224/83

Abstract: The invention provides a semiconductor device low in height and having low heat resistance, and a method of manufacturing the semiconductor device. Disclosed is a semiconductor device including: a support plate 1; a semiconductor chip 2 mounted on one principal surface of the support plate 1 via an adhesive layer, with the element circuit surface of the chip being directed upward; an insulation material layer 4 that seals the semiconductor chip 2 and the periphery of the semiconductor chip; openings formed on an electrode arranged on the element circuit surface of the semiconductor chip 2 in the insulation material layer 4; conductive portions 6 formed in the openings so as to be connected to the electrode of the semiconductor chip; a wiring layer 5 formed on the insulation material layer 4 so as to be connected to the conductive portions 6 and partially extending to the peripheral region of the semiconductor chip 2; and external electrodes 7 formed on the wiring layer 5, wherein the support plate 1 is a flat plate that constitutes the outermost layer of a combined support plate and is separated from the combined support plate in which a plurality of flat plates used in the process of manufacturing the semiconductor device is laminated to each other.

Abstract translation: 本发明提供了一种半导体器件的高度低，耐热性低的半导体器件，以及半导体器件的制造方法。 公开了一种半导体器件，包括：支撑板1; 半导体芯片2，其经由粘合剂层安装在支撑板1的一个主表面上，芯片的元件电路表面朝向上方; 绝缘材料层4，其密封半导体芯片2和半导体芯片的周围; 形成在绝缘材料层4上的布置在半导体芯片2的元件电路表面上的电极上的开口; 形成在开口中以与半导体芯片的电极连接的导电部分6; 形成在绝缘材料层4上的布线层5，以连接到导电部分6并且部分地延伸到半导体芯片2的周边区域; 以及形成在布线层5上的外部电极7，其中支撑板1是构成组合的支撑板的最外层的平板，并且与组合的支撑板分离，在该组合的支撑板中使用多个平板 制造半导体器件彼此层叠。