公开(公告)号：US08964446B2

公开(公告)日：2015-02-24

申请号：US14274616

申请日：2014-05-09

Applicant: Radiant Technologies, Inc.

Inventor： Joseph T. Evans ,  Calvin B. Ward

IPC: G11C11/22

CPC classification number: G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  G11C11/5657 ,  G11C27/005

Abstract: A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states. A read circuit measures the charge stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the read line to generate an output value, the output value corresponding to one of the states.

Abstract translation: 公开了具有多个铁电存储单元的铁电存储器，每个强电介质存储单元包括铁电电容器。 铁电存储器包括读写线和多个铁电存储器单元选择总线，每个铁电存储单元相应的一个选择总线。 每个铁电存储单元包括用于响应于与该铁电存储单元相对应的强电介质存储单元选择总线上的信号而分别将铁电存储单元连接到读取线和写入线的第一和第二栅极。 写入电路使电荷存储在当前连接到写入线的强电介质存储单元的铁电电容器中，电荷具有由具有至少三个状态的数据值确定的值。 读取电路测量存储在当前连接到读取线的铁电存储器单元的铁电电容器中的电荷，以产生与其中一个状态对应的输出值。

公开(公告)号：US20140334220A1

公开(公告)日：2014-11-13

申请号：US14338153

申请日：2014-07-22

Applicant: Radiant Technologies, Inc.

Inventor： Joseph T. Evans

IPC: G11C11/22

CPC classification number: H03K19/0008 ,  G11C7/1006 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2297 ,  H03K19/096

Abstract: A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts. In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.

Abstract translation: 公开了具有自主铁电存储器锁存器（AML）的电路。 AML以AML输入，AML输出，第一AML电源触点，第二AML电源触点和AML状态为特征，以及与AML输入或AML输出之一串联的第一开关。 开关被定位成在第一和第二AML电源触点之间提供电力时防止AML的状态改变。 在本发明的一个方面，电路可以包括与AML输入或AML输出中的另一个串联的第二开关和与AML输入或AML输出串联的锁存器。 锁存器的定位使得AML输出和AML输入之间不存在直接回路。

公开(公告)号：EP2870604B1

公开(公告)日：2018-11-14

申请号：EP13813880.5

申请日：2013-07-01

Applicant: Radiant Technologies, Inc.

Inventor： EVANS, Joseph, T.

IPC: G11C11/22 ,  G11C14/00 ,  G11C5/14 ,  G11C7/24 ,  G11C8/20 ,  G11C16/22 ,  G11C7/20 ,  G11C7/10 ,  G11C19/00 ,  H01L27/11502 ,  H03K3/356

CPC classification number: G11C5/148 ,  G11C7/1006 ,  G11C7/20 ,  G11C7/24 ,  G11C8/20 ,  G11C11/221 ,  G11C14/00 ,  G11C16/22 ,  G11C19/005 ,  H01L27/11502 ,  H03K3/356008

Abstract: A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts, In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.

公开(公告)号：EP0946989A1

公开(公告)日：1999-10-06

申请号：EP97936225.0

申请日：1997-07-25

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： EVANS, Joseph, T., Jr.

IPC: H01L21 ,  H01L27 ,  H01L29

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75 ,  H01L29/516

Abstract: A ferroelectric memory cell (200) for storing information. The information is stored in the remnant polarization of a ferroelectric dielectric layer (213) by setting the direction of the remnant polarization. The ferroelectric memory cell (200) is designed to store the information at a temperature less than a first temperature. The memory cell (200) includes top and bottom contacts that sandwich the dielectric layer (213) which includes a ferroelectric material having a Curie point greater than the first temperature and less than 400 degrees C. The dielectric layer (213) is encapsulated in an oxygen impermeable material such that the encapsulating layer (221) prevents oxygen from entering or leaving the dielectric layer (213). One of the contacts typically includes a platinum electrode (210). The other contact may include a similar electrode or a semiconductor layer having electrodes spaced apart thereon.

公开(公告)号：EP0528961A1

公开(公告)日：1993-03-03

申请号：EP91910220.0

申请日：1991-05-06

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： EVANS, Joseph, Tate, Jr. ,  BULLINGTON, Jeff, Allen

IPC: G02F1 ,  G02B6

CPC classification number: G02B6/3522 ,  G02B6/355 ,  G02B6/3596 ,  G02F1/0126 ,  G02F1/293 ,  G02F1/3137

Abstract: Dispositif de commutation photo-activé (10) dans lequel la réception d'un signal de lumière sert à commuter un faisceau de lumière entre deux points de sortie (14) et (16). Le faisceau de lumière d'entrée est réfléchi par une interface située entre deux régions d'indices de réfraction différents, lorsque le signal de lumière est présent. Ensuite, le faisceau de lumière réfléchi sort par le premier point de sortie (16). En l'absence du signal de lumière, les deux régions ont le même indice de réfraction, et le faisceau de lumière passe par les deux régions et il sort par le second point de sortie (14).

公开(公告)号：EP1915828A1

公开(公告)日：2008-04-30

申请号：EP06768911.7

申请日：2006-06-16

Applicant: Radiant Technologies, Inc.

Inventor： KIM, Tae Il ,  LEE, Hee Man ,  HA, Tae Joon ,  KWON, Tae Kyoung ,  LEE, Jeong Keun

IPC: H04B7/26

CPC classification number: H04W64/00 ,  G01S5/0205 ,  G01S5/14

Abstract: A method of determining a location of a mobile communication terminal, the method including: receiving base station identification signals from a plurality of base stations; calculating distance ratios between the plurality of base stations and the mobile communication terminal, from the received base station identification signals; generating first variables and second variables from the distance ratios; and determining the location of the mobile communication terminal from the first variables and the second variables is provided.

公开(公告)号：EP0815596B1

公开(公告)日：2001-08-22

申请号：EP96908703.0

申请日：1996-03-09

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： EVANS, Joseph, Tate, Jr. ,  WARREN, William, L. ,  TUTTLE, Bruce, A.

IPC: H01L29/78 ,  H01L29/51

CPC classification number: H01L29/516 ,  G11C11/223

Abstract: An improved ferroelectric FET structure (10) in which the ferroelectric layer (14) is doped to reduce retention loss. A ferroelectric FET according to the present invention includes a semiconductor layer (16) having first and second contacts (18, 19) thereon, the first and second contacts being separated from one another. The ferroelectric FET also includes a bottom electrode (12) and a ferroelectric layer (14) which is sandwiched between the semiconductor layer (16) and the bottom electrode (12). The ferroelectric layer (14) is constructed from a perovskite structure of the chemical composition ABO3 wherein the B site comprises first and second elements and a dopant element that has an oxidation state greater than +4 in sufficient concentration to impede shifts in the resistance measured between the first and second contacts with time. The ferroelectric FET structure preferably comprises Pb in the A-site. The first and second elements are preferably Zr and Ti, respectively. The preferred B-site dopants are Niobium, Tantalum, and Tungsten at concentration between 1 % and 8 %.

公开(公告)号：EP0815590A4

公开(公告)日：1999-08-25

申请号：EP96908739

申请日：1996-03-08

Applicant: RADIANT TECHNOLOGIES INC

Inventor： EVANS JOSEPH TATE JR ,  BOYER LENARD

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L21/44

CPC classification number: H01L28/60 ,  H01L28/55 ,  Y10S148/014 ,  Y10S148/10

Abstract: A method for making an improved LSCO stack in the generation of small platinum features (46) on the surface of a substrate (32) by sputtering of the LSCO material (54) and utilizing a photoresist mask to pattern the LSCO (54) in accordance with the platinum features (46). The problems and expense associated with high-temperature deposition of LSCO on platinum and the etching thereof are overcome by sputtering the LSCO at room temperature.

公开(公告)号：EP0815596A4

公开(公告)日：1998-06-03

申请号：EP96908703

申请日：1996-03-09

Applicant: RADIANT TECHNOLOGIES INC

Inventor： EVANS JOSEPH TATE JR ,  WARREN WILLIAM L ,  TUTTLE BRUCE A

IPC: H01L21/8247 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

CPC classification number: H01L29/516 ,  G11C11/223

Abstract: An improved ferroelectric FET structure (10) in which the ferroelectric layer (14) is doped to reduce retention loss. A ferroelectric FET according to the present invention includes a semiconductor layer (16) having first and second contacts (18, 19) thereon, the first and second contacts being separated from one another. The ferroelectric FET also includes a bottom electrode (12) and a ferroelectric layer (14) which is sandwiched between the semiconductor layer (16) and the bottom electrode (12). The ferroelectric layer (14) is constructed from a perovskite structure of the chemical composition ABO3 wherein the B site comprises first and second elements and a dopant element that has an oxidation state greater than +4 in sufficient concentration to impede shifts in the resistance measured between the first and second contacts with time. The ferroelectric FET structure preferably comprises Pb in the A-site. The first and second elements are preferably Zr and Ti, respectively. The preferred B-site dopants are Niobium, Tantalum, and Tungsten at concentration between 1 % and 8 %.

Abstract translation: 改进的铁电FET结构，其中掺杂铁电层以减少保留损耗。 根据本发明的铁电FET包括其上具有第一和第二触点的半导体层，第一和第二触点彼此分离。 铁电FET还包括夹在半导体层和底部电极之间的底部电极和铁电体层。 铁电层由化学组成ABO 3的钙钛矿结构构成，其中B位置包含第一和第二元素以及具有足够浓度的大于+4的氧化态的掺杂剂元素，以阻止在第一和第二元素之间测量的电阻的偏移 第二次接触时间。 铁电FET结构优选在A位置包含Pb。 第一和第二元素分别优选为Zr和Ti。 优选的B位掺杂剂是浓度在1％和8％之间的铌，钽和钨。

公开(公告)号：EP0815590A1

公开(公告)日：1998-01-07

申请号：EP96908739.0

申请日：1996-03-08

Applicant: RADIANT TECHNOLOGIES, INC.

Inventor： EVANS, Joseph, Tate, Jr. ,  BOYER, Lenard

IPC: H01L21 ,  H01L27

CPC classification number: H01L28/60 ,  H01L28/55 ,  Y10S148/014 ,  Y10S148/10

Abstract: A method for making an improved LSCO stack in the generation of small platinum features (46) on the surface of a substrate (32) by sputtering of the LSCO material (54) and utilizing a photoresist mask to pattern the LSCO (54) in accordance with the platinum features (46). The problems and expense associated with high-temperature deposition of LSCO on platinum and the etching thereof are overcome by sputtering the LSCO at room temperature.