公开(公告)号：EP1811370A2

公开(公告)日：2007-07-25

申请号：EP06027048.5

申请日：2006-12-29

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Kapil, Batra

IPC: G06F5/06 ,  G06F5/16

CPC classification number: G06F5/065 ,  G06F5/16 ,  G11C7/1075

Abstract: The present invention related to a first-in first-out (FIFO) memory architecture (10, 20) providing multiport functionality and comprising:
- a plurality of single-port memory structures (11, 21a, 21b);
- an indexing block (12, 22) for storing information about a single-port memory structure (11, 21a, 21b) in which incoming data is being stored in each data write operation; and
- an access controller (13, 23) for controlling operations on the single-port memory structures (11, 21a, 21b) based on the contents of the indexing block (12, 22).
A method of operating a plurality of single port memory structures (11, 21a, 21b) as a FIFO multiport memory architecture (10, 20) for sequential memory operations is also described.

Abstract translation: 本发明涉及提供多端口功能的先进先出（FIFO）存储器架构（10,20），并且包括： - 多个单端口存储器结构（11,21a，21b）; - 索引块（12,22），用于存储关于在每个数据写入操作中存储输入数据的单端口存储器结构（11,21a，21b）的信息; 以及 - 用于基于所述分度块（12,22）的内容来控制对所述单端口存储器结构（11,21a，21b）的操作的访问控制器（13,23）。 还描述了操作用于顺序存储器操作的多个单端口存储器结构（11,21a，21b）作为FIFO多端口存储器架构（10,20）的方法。

公开(公告)号：EP1259079B1

公开(公告)日：2007-03-21

申请号：EP02008699.7

申请日：2002-04-18

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chelladurai, Paul, Sathya ,  Ahmed, Arshad ,  Nandy, Soumitra, Kumar

IPC: H04N7/26

CPC classification number: H04N19/53 ,  H04N19/14 ,  H04N19/194 ,  H04N19/61

公开(公告)号：EP1727156A2

公开(公告)日：2006-11-29

申请号：EP06114150.3

申请日：2006-05-18

Applicant: STMicroelectronics Pvt. Ltd

Inventor： DUBEY, Prashant

IPC: G11C29/02

CPC classification number: G11C29/02 ,  G11C5/025 ,  G11C29/024 ,  G11C2029/1206

Abstract: The invention provides an integrated test device thereby reducing external wiring congestion to the memory. The integrated test device provides for separate decoder testing and debugging to find specific errors in the memory. The device also helps in reducing the complexity of the test of external BIST. Furthermore, the number of clock cycles required for the decoder testing for an N-address memory is reduced from 4N cycles to N clock cycles. Additionally, the access time for the memory is reduced as the test device is used as a pipelining device in normal operation mode.

Abstract translation: 本发明提供一种集成的测试装置，从而减少对存储器的外部布线拥塞。 集成测试设备提供单独的解码器测试和调试，以发现存储器中的特定错误。 该器件还有助于降低外部BIST测试的复杂性。 此外，N寻址存储器的解码器测试所需的时钟周期数从4N周期减少到N个时钟周期。 此外，随着测试设备在正常操作模式下用作流水线设备，存储器的访问时间减少。

公开(公告)号：EP1679797A1

公开(公告)日：2006-07-12

申请号：EP05028707.7

申请日：2005-12-30

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Gupta, Ranjeet ,  Garg, Paras

IPC: H03K19/003 ,  H03K17/16

CPC classification number: H03K17/162 ,  H03K19/00361

Abstract: The invention relates to a low noise output buffer capable of operating at high speeds which allows a control of the slew rate at the raising and falling edges of an input signal (A) of the buffer. The proposed low noise output buffer (5) is inserted between first and second voltage references (VDD, GND) and comprises a main circuit (50) for which the slew rate of an input signal (A) is to be controlled, the main circuit (50) being connected to a slew rate control circuit (52), in turn inserted between the first and second voltage references (VDD, GND). Advantageously according to the invention, the slew rate control circuit (52) comprises an additional circuit (51) connected to the main circuit (50) and operating a slew rate limiting at the raising and falling edges of the input signal (A) of the low noise output buffer (5).

Abstract translation: 本发明涉及一种能够高速运行的低噪声输出缓冲器，其允许控制缓冲器的输入信号（A）的上升沿和下降沿的转换速率。 所提出的低噪声输出缓冲器（5）插入在第一和第二参考电压（VDD，GND）之间，并且包括一个主电路（50），用于输入信号（A）的转换速率被控制，主电路 （50）连接到压摆率控制电路（52），然后插入在第一和第二参考电压（VDD，GND）之间。 有利地，根据本发明，转换速率控制电路（52）包括连接到主电路（50）的附加电路（51），并且操作在输入信号（A）的上升沿和下降沿的转换速率限制 低噪声输出缓冲器（5）。

公开(公告)号：EP1677175A2

公开(公告)日：2006-07-05

申请号：EP05113079.7

申请日：2005-12-29

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Uguen, Laurent ,  Dhiman, Gaurav ,  Kapoor, Gaurav

IPC: G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/3203 ,  G06F1/3287 ,  Y02D10/128 ,  Y02D10/171 ,  Y02D50/20

Abstract: A system for dynamic power management in a distributed architecture system on chip, comprising a means for dynamically defining the feasibility of entering a low power mode of operation based on the status of components of the system, a means for entering or exiting safely from a low power state based on said feasibility, a means for decreasing the power centric communication between various processors and a means for increasing the low power mode time. Thus a framework is proposed in the instant invention wherein all the device drivers dynamically maintain the information on the feasibility of a low power transition at any point of time. Thus whenever an opportunity to enter a low power mode comes up one has to just check this feasibility variable to determine whether the low power mode entry is viable or not. For ensuring the safe transition to a low power mode, a stalling machine is proposed in case of DSPs. For further saving power, a power centric communication channel is established between various processors and to reduce the load on this communication channel techniques like quad-ring buffer and DSP feedback are proposed.

Abstract translation: 一种用于分布式架构系统中的动态功率管理的系统，包括用于基于所述系统的部件的状态动态地定义进入低功率操作模式的可行性的装置，用于从低速进入或退出安全的装置 基于所述可行性的功率状态，用于减小各种处理器之间的功率中心通信的手段和用于增加低功率模式时间的手段。 因此，在本发明中提出了一种框架，其中所有设备驱动程序在任何时间点动态地维护关于低功率转换的可行性的信息。 因此，每当有机会进入低功耗模式时，只能检查这个可行性变量来确定低功耗模式输入是否可行。 为了确保安全地转换到低功耗模式，在DSP的情况下，提出了一种停滞的机器。 为了进一步节约能源，在各种处理器之间建立了一个以电力为中心的通信通道，并且减少了这种通信信道的负载，如四环缓冲器和DSP反馈。

公开(公告)号：EP1667004A2

公开(公告)日：2006-06-07

申请号：EP05111142.5

申请日：2005-11-23

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chatterjee, Kallol ,  Sreekiran, Samala

IPC: G05F3/24

CPC classification number: G05F3/242

Abstract: An improved first order temperature compensated reference current generator. It comprises a current device providing a controlled current, a startup circuit connected to said current device for initiating operation of said current device, and a current definition mechanism driven by said current device for supplying a current which is independent of temperature, process and individual temperature coefficients circuit elements used. The said current definition mechanism incorporates voltage controlled resistors driven by a predetermined voltage and having a predetermined temperature coefficient.

Abstract translation: 改进的一阶温度补偿参考电流发生器。 其包括提供受控电流的电流装置，连接到所述电流装置的启动电路，用于启动所述电流装置的运行，以及由所述电流装置驱动的电流定义机构，用于提供独立于温度，过程和个别温度的电流 系数电路元件使用。 所述电流定义机构包括由预定电压驱动且具有预定温度系数的压控电阻。

公开(公告)号：EP1324619B1

公开(公告)日：2006-05-17

申请号：EP02022752.6

申请日：2002-10-11

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Chakravarthy, Kalyana, Flat No. 7

IPC: H04N7/62 ,  H04N7/56 ,  H03L7/197 ,  H04N5/12 ,  H03L7/00

CPC classification number: H04N21/4305 ,  H03L7/0992 ,  H03L7/181

公开(公告)号：EP1492234A3

公开(公告)日：2006-03-15

申请号：EP04014644.1

申请日：2004-06-22

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Roy, Amit

IPC: H03K17/22

CPC classification number: H03K17/223 ,  H03K2217/0036

Abstract: The present invention provides an improved Power-On-reset (POR) circuit providing enhanced reliability and automatic power-down capability, comprising a supply voltage sensing circuit (IS1,P1,VCCS), a delay element (1) connected to the output of the supply voltage sensing circuit, and a switch (P2,N2) that activates the output POR signal when the output of the delay element indicates a reduced supply voltage and deactivates the POR output and provides feedback to reduce current through the supply voltage sensing circuit once the supply voltage is normal.

公开(公告)号：EP1630958A2

公开(公告)日：2006-03-01

申请号：EP05018679.0

申请日：2005-08-29

Applicant: STMicroelectronics Pvt. Ltd

Inventor： Bhuvanagiri, Aditha ,  Singh, Halvinder ,  Malik, Rakesh

IPC: H03H17/06

CPC classification number: H03H17/0275 ,  H03H17/0657

Abstract: A minimal area integrated circuit implementation of a polyphase interpolation filter using symmetry of coefficients for at least one channel of input data, comprising, an input interface block for synchronizing the input signal to a first internal clock signal; a memory block for providing multiple delayed output signals; a channel select multiplexer block selecting a channel in response to a first set of internal control signals; a multiplexer input interface block for outputting a selected plurality of signals for generating mirror image coefficient sets in response to a second set of internal control signals, a coefficient block for generating mirror image and/or symmetric coefficient sets, and to output a plurality of filtered signals , an output multiplexer block for performing selection, gain control and data width control on said plurality of filtered signals, an output register block for synchronization of filtered signal, and a control block to generate clock signals for realization of the filter and to delay between two channels to access a coefficient set, thereby minimizing hardware requirement of coefficient set implementation in a polyphase interpolation filter.

Abstract translation: 的最小面积集成电路实施方式使用系数的输入数据的至少一个信道，在输入接口块，包括用于同步输入信号到第一内部时钟信号的对称性的多相内插滤波器的; 用于提供多延迟输出信号的存储器块; 一信道选择复用器块选择响应于第一组内部控制信号的信道; 用于输出铃声复用器输入接口块的信号，用于响应于第二组内部控制信号的生成镜像系数集合，用于产生镜像和/或对称的系数组的系数块，并且输出的过滤的多个选择的多个 信号，以输出多路转换器块，用于执行选择，增益控制和数据宽度控制对所述多个经滤波的信号的输出寄存器块为滤波后的信号的同步，以及控制块，为实现滤波器的生成时钟信号，并延时之间 两个信道来访问的一组系数，从而最小化在一多相内插滤波器系数集合执行硬件要求。

公开(公告)号：EP1538596A2

公开(公告)日：2005-06-08

申请号：EP04028541.3

申请日：2004-12-02

Applicant: STMicroelectronics Pvt. Ltd. ,  STMicroelectronics GmbH

Inventor： Khurana, Jatin ,  Gourdou, Yvon

IPC: G09G3/36

CPC classification number: G09G3/3622 ,  G09G3/18 ,  G09G3/2014 ,  G09G3/2018 ,  G09G3/3614 ,  G09G2310/06 ,  G09G2320/0204 ,  G09G2320/0626 ,  G09G2320/066

Abstract: An LCD display driver providing adjustable contrast independently of multiplexing requirements by generating each COM signal in a time slot of a repeating signal frame, each COM signal containing one or more active periods and one or more inactive periods, the relative time proportions of which are adjustable, and corresponding SEGMENT signals turn on/off required segments while maintaining an essentially zero DC component, the logic levels and the relative active time and inactive times of the COM and segment signals being adjustable for increasing or decreasing the RMS voltage levels across the LCD element as desired.

Abstract translation: 一种LCD显示驱动器，通过在重复信号帧的时隙中产生每个COM信号来提供独立于复用要求的可调对比度，每个COM信号包含一个或多个有效周期和一个或多个非活动时段，其相对时间比例可调 ，并且相应的SEGMENT信号打开/关闭所需的段，同时保持基本为零的DC分量，COM和段信号的逻辑电平和相对有效时间和无效时间是可调节的，用于增加或减少跨越LCD元件的RMS电压电平 如预期的。